mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 10:30:32 +00:00
3b52847a45
microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlr1ldMACgkQykllyylKDCHioACghoJw6+NqsZXl8zGWRP38yZ5K mvgAnihfOQq125mpKPZmcc5yt6wVwYIU =8ji9 -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup |
||
|---|---|---|
| .. | ||
| zynq-cc108 | ||
| zynq-microzed | ||
| zynq-zc702 | ||
| zynq-zc706 | ||
| zynq-zc770-xm010 | ||
| zynq-zc770-xm011 | ||
| zynq-zc770-xm011-x16 | ||
| zynq-zc770-xm012 | ||
| zynq-zc770-xm013 | ||
| zynq-zed | ||
| zynq-zybo | ||
| .gitignore | ||
| board.c | ||
| MAINTAINERS | ||
| Makefile | ||
| xil_io.h | ||
| zynq-cse-qspi-single | ||