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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
395 lines
15 KiB
C
395 lines
15 KiB
C
/*
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* (C) Copyright 2000
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* Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Config header file for Cogent platform using an MPC8xx CPU module
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
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#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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#define CONFIG_SYS_TEXT_BASE 0xfff00000
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#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
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#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
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/* Cogent Modular Architecture options */
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#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
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#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere (for example, on the cogent platform, there are serial
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* ports on the motherboard which are used for the serial console - see
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* cogent/cma101/serial.[ch]).
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*/
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#define CONFIG_CONS_ON_SMC /* define if console on SMC */
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#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else*/
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#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
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#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
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#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
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#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
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#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
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#define CONFIG_ETHER_NONE /* define if ether on something else */
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#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
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/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
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#define CONFIG_8260_CLKIN 66666666 /* in Hz */
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#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
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#define CONFIG_BAUDRATE 230400
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#else
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#define CONFIG_BAUDRATE 9600
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_KGDB
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#ifdef DEBUG
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
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#define CONFIG_BOOTARGS "root=/dev/ram rw"
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
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#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
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#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
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#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
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#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
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#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
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#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
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# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
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# else
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#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
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# endif
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#endif
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#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Low Level Cogent settings
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* if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
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* also, make sure CONFIG_CONS_INDEX is still defined - the index will be
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* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
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* (second 2 for CMA120 only)
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*/
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#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
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#include <configs/cogent_common.h>
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#ifdef CONFIG_CONS_NONE
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#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
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#endif
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#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
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#define CONFIG_SHOW_ACTIVITY
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#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
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/*
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* flash exists on the motherboard
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* set these four according to TOP dipsw:
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* TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
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* TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
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*/
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#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
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#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
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#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
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#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
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#endif
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#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
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#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*
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* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
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* defines for the various registers affected by the HRCW e.g. changing
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* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
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*/
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#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
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HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
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/* no slaves so just duplicate the master hrcw */
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#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
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#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
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#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
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#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
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#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
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#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
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#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xF0000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
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#ifdef CONFIG_CMA302
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#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
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#else
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#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
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#endif
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
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#ifdef CONFIG_CMA302
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#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
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#else
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
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#endif
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
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* but Soft reset does not.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
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HID0_IFEM|HID0_ABE)
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#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
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#define CONFIG_SYS_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CONFIG_SYS_RMR RMR_CSRE
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_BCR BCR_EBM
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 4-35
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
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SYPCR_SWRI|SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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* Ensure DFBRG is Divide by 16
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*/
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#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RCCR 0
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#if defined(CONFIG_CMA282)
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/*
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* Init Memory Controller:
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*
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* According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
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* and CS2 for (optional) local bus RAM on the CPU module.
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*
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* Note the motherboard address space (256 Mbyte in size) is connected
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* to the 60x Bus and is located starting at address 0. The Hard Reset
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* Configuration Word should put the 60x Bus into External Bus Mode, since
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* we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
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*
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* (the *_SIZE vars must be a power of 2)
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*/
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#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
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#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
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#if 0
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#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
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#define CONFIG_SYS_CMA_CS2_SIZE (16 << 20)
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#endif
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/*
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* CS0 maps the EPROM on the cpu module
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* Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
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*
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* Note: We must have already transferred control to the final location
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* of the EPROM before these are used, because when BR0/OR0 are set, the
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* mirror of the eprom at any other addresses will disappear.
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*/
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/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
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/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
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#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
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ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
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/*
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* CS2 enables the Local Bus SDRAM on the CPU Module
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*
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* Will leave this unset for the moment, because a) my CPU module has no
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* SDRAM installed (it is optional); and b) it will require programming
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* one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
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* if you can't test it.
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*/
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#if 0
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/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
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/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
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#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
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#endif
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#endif
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#endif /* __CONFIG_H */
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