mirror of
https://github.com/AsahiLinux/u-boot
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4157c472c3
Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.12-rc6, commit 6f7da290413ba713f0cdd9ff1a2a9bb129ef4f6c . This includes both M3 and H3 ULCB and Salvator-X boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
70 lines
2 KiB
C
70 lines
2 KiB
C
/*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a7795 CPG Core Clocks */
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#define R8A7795_CLK_Z 0
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#define R8A7795_CLK_Z2 1
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#define R8A7795_CLK_ZR 2
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#define R8A7795_CLK_ZG 3
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#define R8A7795_CLK_ZTR 4
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#define R8A7795_CLK_ZTRD2 5
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#define R8A7795_CLK_ZT 6
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#define R8A7795_CLK_ZX 7
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#define R8A7795_CLK_S0D1 8
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#define R8A7795_CLK_S0D4 9
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#define R8A7795_CLK_S1D1 10
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#define R8A7795_CLK_S1D2 11
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#define R8A7795_CLK_S1D4 12
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#define R8A7795_CLK_S2D1 13
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#define R8A7795_CLK_S2D2 14
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#define R8A7795_CLK_S2D4 15
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#define R8A7795_CLK_S3D1 16
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#define R8A7795_CLK_S3D2 17
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#define R8A7795_CLK_S3D4 18
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#define R8A7795_CLK_LB 19
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#define R8A7795_CLK_CL 20
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#define R8A7795_CLK_ZB3 21
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#define R8A7795_CLK_ZB3D2 22
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#define R8A7795_CLK_CR 23
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#define R8A7795_CLK_CRD2 24
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#define R8A7795_CLK_SD0H 25
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#define R8A7795_CLK_SD0 26
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#define R8A7795_CLK_SD1H 27
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#define R8A7795_CLK_SD1 28
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#define R8A7795_CLK_SD2H 29
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#define R8A7795_CLK_SD2 30
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#define R8A7795_CLK_SD3H 31
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#define R8A7795_CLK_SD3 32
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#define R8A7795_CLK_SSP2 33
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#define R8A7795_CLK_SSP1 34
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#define R8A7795_CLK_SSPRS 35
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#define R8A7795_CLK_RPC 36
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#define R8A7795_CLK_RPCD2 37
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#define R8A7795_CLK_MSO 38
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#define R8A7795_CLK_CANFD 39
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#define R8A7795_CLK_HDMI 40
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#define R8A7795_CLK_CSI0 41
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#define R8A7795_CLK_CSIREF 42
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#define R8A7795_CLK_CP 43
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#define R8A7795_CLK_CPEX 44
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#define R8A7795_CLK_R 45
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#define R8A7795_CLK_OSC 46
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/* r8a7795 ES2.0 CPG Core Clocks */
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#define R8A7795_CLK_S0D2 47
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#define R8A7795_CLK_S0D3 48
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#define R8A7795_CLK_S0D6 49
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#define R8A7795_CLK_S0D8 50
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#define R8A7795_CLK_S0D12 51
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#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
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