Icenowy Zheng ec4670a137 sunxi: add LPDDR3 timing from stock boot0 ... As we added LPDDR3 support in the former patch, we need a set of timing info to really enable it. Add the timing info used by stock boot0. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>		2017-06-08 22:37:55 +05:30
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dram_timings	sunxi: add LPDDR3 timing from stock boot0	2017-06-08 22:37:55 +05:30
board.c	sunxi: i2c: Add support for DM I2C	2017-04-28 09:19:03 +02:00
clock.c	sunxi: add gtbus-initialisation for sun9i	2016-10-30 11:38:04 +01:00
clock_sun4i.c
clock_sun6i.c	sunxi: add clock configuration of R40 sata	2017-05-02 09:21:09 +02:00
clock_sun8i_a83t.c
clock_sun9i.c	sunxi: add initial clock setup for sun9i for SPL	2016-10-30 11:38:04 +01:00
cpu_info.c	sunxi: add basic V3s support	2017-04-21 09:23:17 +02:00
dram_helpers.c	ARM: Rework and correct barrier definitions	2016-08-05 07:23:57 -04:00
dram_sun4i.c
dram_sun6i.c
dram_sun8i_a23.c
dram_sun8i_a33.c
dram_sun8i_a83t.c
dram_sun9i.c	sunxi: DRAM initialisation for sun9i	2016-10-30 11:38:04 +01:00
dram_sunxi_dw.c	sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller	2017-06-08 22:37:55 +05:30
gtbus_sun9i.c	sunxi: add gtbus-initialisation for sun9i	2016-10-30 11:38:04 +01:00
Kconfig	sunxi: add LPDDR3 timing from stock boot0	2017-06-08 22:37:55 +05:30
Makefile	sunxi: Add selective DRAM type and timing	2017-06-08 22:37:55 +05:30
p2wi.c
pinmux.c
pmic_bus.c	sunxi: Enable AXP221s in I2C mode with the R40 SoC	2017-04-20 13:30:00 +02:00
prcm.c
rmr_switch.S	sunxi: A64: do an RMR switch if started in AArch32 mode	2017-01-04 16:37:42 +01:00
rsb.c
usb_phy.c	sunxi: prepare for sharing MACH_SUN8I_H3 config symbol	2017-04-05 15:03:17 +05:30