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https://github.com/AsahiLinux/u-boot
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56882dc4cb
On mvebu this is defined if and only if !ARM64. Otherwise it is defined for boards with ARCH_MX23, ARCH_TEGRA and ARCH_ZYNQ, and also for SOC_AR934X (tplink_wdr4300). Signed-off-by: Marek Behún <marek.behun@nic.cz>
62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#ifndef _CONFIG_DB_88F6720_H
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#define _CONFIG_DB_88F6720_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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/*
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* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
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* for DDR ECC byte filling in the SPL before loading the main
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* U-Boot into it.
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*/
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/* I2C */
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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/* USB/EHCI configuration */
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
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/* Environment in SPI NOR flash */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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*/
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#include "mv-common.h"
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/*
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* Memory layout while starting into the bin_hdr via the
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* BootROM:
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*
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* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
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* 0x4000.4030 bin_hdr start address
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* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
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* 0x4007.fffc BootROM stack top
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*
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* The address space between 0x4007.fffc and 0x400f.fff is not locked in
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* L2 cache thus cannot be used.
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*/
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MALLOC_SIMPLE
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#endif
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#endif /* _CONFIG_DB_88F6720_H */
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