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https://github.com/AsahiLinux/u-boot
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0c9075e9ad
Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
179 lines
4 KiB
C
179 lines
4 KiB
C
/*
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* From Coreboot file of same name
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*
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ARCH_ASM_LAPIC_H
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#define _ARCH_ASM_LAPIC_H
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#include <asm/io.h>
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#include <asm/lapic_def.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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/* See if I need to initialize the local apic */
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#if CONFIG_SMP || CONFIG_IOAPIC
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# define NEED_LAPIC 1
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#else
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# define NEED_LAPIC 0
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#endif
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static inline __attribute__((always_inline))
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unsigned long lapic_read(unsigned long reg)
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{
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return readl(LAPIC_DEFAULT_BASE + reg);
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}
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static inline __attribute__((always_inline))
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void lapic_write(unsigned long reg, unsigned long val)
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{
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writel(val, LAPIC_DEFAULT_BASE + reg);
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}
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static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
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{
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do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
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}
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static inline void enable_lapic(void)
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{
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msr_t msr;
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msr = msr_read(LAPIC_BASE_MSR);
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msr.hi &= 0xffffff00;
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msr.lo |= LAPIC_BASE_MSR_ENABLE;
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msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
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msr.lo |= LAPIC_DEFAULT_BASE;
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msr_write(LAPIC_BASE_MSR, msr);
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}
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static inline void disable_lapic(void)
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{
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msr_t msr;
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msr = msr_read(LAPIC_BASE_MSR);
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msr.lo &= ~(1 << 11);
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msr_write(LAPIC_BASE_MSR, msr);
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}
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static inline __attribute__((always_inline)) unsigned long lapicid(void)
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{
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return lapic_read(LAPIC_ID) >> 24;
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}
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#if !CONFIG_AP_IN_SIPI_WAIT
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/* If we need to go back to sipi wait, we use the long non-inlined version of
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* this function in lapic_cpu_init.c
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*/
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static inline __attribute__((always_inline)) void stop_this_cpu(void)
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{
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/* Called by an AP when it is ready to halt and wait for a new task */
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for (;;)
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cpu_hlt();
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}
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#else
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void stop_this_cpu(void);
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#endif
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#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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: "=q" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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}
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return x;
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}
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static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
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{
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(void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
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}
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#ifdef X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define lapic_read_around(x) lapic_read(x)
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# define lapic_write_around(x, y) lapic_write((x), (y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define lapic_read_around(x) lapic_read(x)
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# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
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#endif
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static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
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{
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int timeout;
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unsigned long status;
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int result;
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lapic_wait_icr_idle();
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
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lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
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timeout = 0;
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do {
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status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
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} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
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result = -1;
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if (status == LAPIC_ICR_RR_VALID) {
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*pvalue = lapic_read(LAPIC_RRR);
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result = 0;
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}
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return result;
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}
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void lapic_setup(void);
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#if CONFIG_SMP
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struct device;
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int start_cpu(struct device *cpu);
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#endif /* CONFIG_SMP */
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int boot_cpu(void);
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/**
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* struct x86_cpu_priv - Information about a single CPU
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*
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* @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
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* just a number representing the CPU core
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*
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* TODO: Move this to driver model once lifecycle is understood
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*/
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struct x86_cpu_priv {
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int apic_id;
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int start_err;
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};
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#endif
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