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6eb15e50f4
ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> |
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| .. | ||
| arcregs.h | ||
| bitops.h | ||
| byteorder.h | ||
| cache.h | ||
| config.h | ||
| errno.h | ||
| global_data.h | ||
| init_helpers.h | ||
| io.h | ||
| linkage.h | ||
| posix_types.h | ||
| ptrace.h | ||
| relocate.h | ||
| sections.h | ||
| string.h | ||
| types.h | ||
| u-boot-arc.h | ||
| u-boot.h | ||
| unaligned.h | ||