mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-29 06:23:07 +00:00
1221ce459d
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
270 lines
14 KiB
C
270 lines
14 KiB
C
/*
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* (C) Copyright 2007-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <i2c.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <netdev.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/4xx_pcie.h>
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#include <linux/errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f (void)
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{
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unsigned long mfr;
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/*----------------------------------------------------------------------+
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* Interrupt controller setup for the Katmai 440SPe Evaluation board.
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*-----------------------------------------------------------------------+
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*-----------------------------------------------------------------------+
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* Interrupt | Source | Pol. | Sensi.| Crit. |
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*-----------+-----------------------------------+-------+-------+-------+
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* IRQ 00 | UART0 | High | Level | Non |
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* IRQ 01 | UART1 | High | Level | Non |
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* IRQ 02 | IIC0 | High | Level | Non |
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* IRQ 03 | IIC1 | High | Level | Non |
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* IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
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* IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
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* IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
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* IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
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* IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
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* IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
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* IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
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* IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
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* IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
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* IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
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* IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
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* IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
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* IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
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* IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
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* IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
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* IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
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* IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
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* IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
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* IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
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* IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
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* IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
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* IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
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* IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
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* IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
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* IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
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* IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
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* IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
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* IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
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*------------------------------------------------------------------------
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* IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
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* IRQ 33 | MAL Serr | High | Level | Non |
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* IRQ 34 | MAL Txde | High | Level | Non |
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* IRQ 35 | MAL Rxde | High | Level | Non |
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* IRQ 36 | DMC CE or DMC UE | High | Level | Non |
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* IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
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* IRQ 38 | MAL TX EOB | High | Level | Non |
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* IRQ 39 | MAL RX EOB | High | Level | Non |
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* IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
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* IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
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* IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
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* IRQ 43 | L2 Cache | Risin | Edge | Non |
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* IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
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* IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
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* IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
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* IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
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* IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
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* IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
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* IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
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* IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
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* IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
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* IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
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* IRQ 54 | DMA Error | High | Level | Non |
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* IRQ 55 | DMA I2O Error | High | Level | Non |
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* IRQ 56 | Serial ROM | High | Level | Non |
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* IRQ 57 | PCIX0 Error | High | Edge | Non |
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* IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
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* IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
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* IRQ 60 | EMAC0 Interrupt | High | Level | Non |
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* IRQ 61 | EMAC0 Wake-up | High | Level | Non |
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* IRQ 62 | Reserved | High | Level | Non |
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* IRQ 63 | XOR | High | Level | Non |
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*-----------------------------------------------------------------------
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* IRQ 64 | PE0 AL | High | Level | Non |
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* IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
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* IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
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* IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
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* IRQ 68 | PE0 TCR | High | Level | Non |
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* IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
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* IRQ 70 | PE0 DCR Error | High | Level | Non |
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* IRQ 71 | Reserved | N/A | N/A | Non |
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* IRQ 72 | PE1 AL | High | Level | Non |
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* IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
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* IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
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* IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
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* IRQ 76 | PE1 TCR | High | Level | Non |
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* IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
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* IRQ 78 | PE1 DCR Error | High | Level | Non |
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* IRQ 79 | Reserved | N/A | N/A | Non |
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* IRQ 80 | PE2 AL | High | Level | Non |
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* IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
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* IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
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* IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
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* IRQ 84 | PE2 TCR | High | Level | Non |
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* IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
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* IRQ 86 | PE2 DCR Error | High | Level | Non |
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* IRQ 87 | Reserved | N/A | N/A | Non |
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* IRQ 88 | External IRQ(5) | Progr | Progr | Non |
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* IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
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* IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
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* IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
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* IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
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* IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
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* IRQ 94 | Reserved | N/A | N/A | Non |
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* IRQ 95 | Reserved | N/A | N/A | Non |
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*-----------------------------------------------------------------------
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* IRQ 96 | PE0 INTA | High | Level | Non |
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* IRQ 97 | PE0 INTB | High | Level | Non |
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* IRQ 98 | PE0 INTC | High | Level | Non |
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* IRQ 99 | PE0 INTD | High | Level | Non |
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* IRQ 100 | PE1 INTA | High | Level | Non |
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* IRQ 101 | PE1 INTB | High | Level | Non |
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* IRQ 102 | PE1 INTC | High | Level | Non |
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* IRQ 103 | PE1 INTD | High | Level | Non |
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* IRQ 104 | PE2 INTA | High | Level | Non |
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* IRQ 105 | PE2 INTB | High | Level | Non |
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* IRQ 106 | PE2 INTC | High | Level | Non |
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* IRQ 107 | PE2 INTD | Risin | Edge | Non |
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* IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
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* IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
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* IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
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* IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
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* IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
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* IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
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* IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
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* IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
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* IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
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* IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
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* IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
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* IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
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* IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
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* IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
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* IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
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* IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
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* IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
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* IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
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* IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
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* IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
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*-----------+-----------------------------------+-------+-------+-------+ */
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/*-------------------------------------------------------------------------+
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* Put UICs in PowerPC440SPemode.
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* Initialise UIC registers. Clear all interrupts. Disable all interrupts.
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* Set critical interrupt values. Set interrupt polarities. Set interrupt
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* trigger levels. Make bit 0 High priority. Clear all interrupts again.
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*------------------------------------------------------------------------*/
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mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
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mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
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mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */
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mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
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mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
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mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/
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mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/
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mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
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mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/
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mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
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mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
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mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
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mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
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mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
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mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/
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mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/
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mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
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mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
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mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
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mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/
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mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/
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mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
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mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */
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mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/
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mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
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mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
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mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/
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mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/
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mfsdr(SDR0_MFR, mfr);
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mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
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mtsdr(SDR0_MFR, mfr);
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mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
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out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);
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out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
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out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
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return 0;
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}
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int checkboard (void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf("Board: Katmai - AMCC 440SPe Evaluation Board");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return 0;
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}
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/*
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* Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
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* board specific values.
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*/
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u32 ddr_wrdtr(u32 default_val) {
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return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
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}
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u32 ddr_clktr(u32 default_val) {
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return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
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}
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#if defined(CONFIG_PCI)
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int board_pcie_card_present(int port)
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{
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u32 val;
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val = in32(GPIO0_IR);
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switch (port) {
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case 0:
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return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));
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case 1:
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return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));
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case 2:
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return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));
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default:
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return 0;
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}
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}
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#endif /* defined(CONFIG_PCI) */
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis);
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return pci_eth_init(bis);
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}
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