mirror of
https://github.com/AsahiLinux/u-boot
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120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_ddr_sdram.h>
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#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
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#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
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#endif
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void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num)
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{
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unsigned int i;
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volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR;
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if (ctrl_num != 0) {
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printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
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return;
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}
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i == 0) {
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out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs0_config, regs->cs[i].config);
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} else if (i == 1) {
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out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs1_config, regs->cs[i].config);
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} else if (i == 2) {
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out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs2_config, regs->cs[i].config);
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} else if (i == 3) {
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out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs3_config, regs->cs[i].config);
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}
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}
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out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
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out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
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#endif
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/*
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* 200 painful micro-seconds must elapse between
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* the DDR clock setup and the DDR config enable.
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*/
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udelay(200);
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asm volatile("sync;isync");
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out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
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asm("sync;isync;msync");
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udelay(500);
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void dma_init(void);
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extern uint dma_check(void);
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extern int dma_xfer(void *dest, uint count, void *src);
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/*
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* Initialize all of memory for ECC, then enable errors.
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*/
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void
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ddr_enable_ecc(unsigned int dram_size)
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{
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uint *p = 0;
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uint i = 0;
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volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
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dma_init();
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for (*p = 0; p < (uint *)(8 * 1024); p++) {
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if (((unsigned int)p & 0x1f) == 0) {
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ppcDcbz((unsigned long) p);
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}
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*p = (unsigned int)CONFIG_MEM_INIT_VALUE;
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if (((unsigned int)p & 0x1c) == 0x1c) {
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ppcDcbf((unsigned long) p);
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}
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}
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dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
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dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
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dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
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dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
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dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
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dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
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dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
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dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
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dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
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dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
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for (i = 1; i < dram_size / 0x800000; i++) {
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dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
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}
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/*
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* Enable errors for ECC.
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*/
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debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
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ddr->err_disable = 0x00000000;
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asm("sync;isync;msync");
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debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
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}
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#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
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