mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
c39f44dc6f
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
/*
|
|
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* Version 2 as published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <common.h>
|
|
|
|
#include <asm/fsl_ddr_sdram.h>
|
|
#include <asm/fsl_ddr_dimm_params.h>
|
|
|
|
void fsl_ddr_board_options(memctl_options_t *popts,
|
|
dimm_params_t *pdimm,
|
|
unsigned int ctrl_num)
|
|
{
|
|
/*
|
|
* Factors to consider for clock adjust:
|
|
* - number of chips on bus
|
|
* - position of slot
|
|
* - DDR1 vs. DDR2?
|
|
* - ???
|
|
*
|
|
* This needs to be determined on a board-by-board basis.
|
|
* 0110 3/4 cycle late
|
|
* 0111 7/8 cycle late
|
|
*/
|
|
popts->clk_adjust = 7;
|
|
|
|
/*
|
|
* Factors to consider for CPO:
|
|
* - frequency
|
|
* - ddr1 vs. ddr2
|
|
*/
|
|
popts->cpo_override = 0;
|
|
|
|
/*
|
|
* Factors to consider for write data delay:
|
|
* - number of DIMMs
|
|
*
|
|
* 1 = 1/4 clock delay
|
|
* 2 = 1/2 clock delay
|
|
* 3 = 3/4 clock delay
|
|
* 4 = 1 clock delay
|
|
* 5 = 5/4 clock delay
|
|
* 6 = 3/2 clock delay
|
|
*/
|
|
popts->write_data_delay = 3;
|
|
|
|
/*
|
|
* Factors to consider for half-strength driver enable:
|
|
* - number of DIMMs installed
|
|
*/
|
|
popts->half_strength_driver_enable = 0;
|
|
}
|