mirror of
https://github.com/AsahiLinux/u-boot
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f10643cf8a
At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
352 lines
7.7 KiB
C
352 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Texas Instruments Incorporated, <www.ti.com>
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* Jean-Jacques Hiblot <jjhiblot@ti.com>
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <log.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <linux/bitops.h>
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#include <linux/ioport.h>
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#include <dm/device-internal.h>
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#include <dm/read.h>
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/arch/mux.h>
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#endif
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struct pbias_reg_info {
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u32 enable;
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u32 enable_mask;
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u32 disable_val;
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u32 vmode;
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unsigned int enable_time;
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char *name;
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};
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struct pbias_priv {
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struct regmap *regmap;
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int offset;
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};
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static const struct pmic_child_info pmic_children_info[] = {
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{ .prefix = "pbias", .driver = "pbias_regulator"},
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{ },
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};
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static int pbias_write(struct udevice *dev, uint reg, const uint8_t *buff,
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int len)
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{
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struct pbias_priv *priv = dev_get_priv(dev);
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u32 val = *(u32 *)buff;
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if (len != 4)
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return -EINVAL;
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return regmap_write(priv->regmap, priv->offset, val);
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}
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static int pbias_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
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{
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struct pbias_priv *priv = dev_get_priv(dev);
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if (len != 4)
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return -EINVAL;
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return regmap_read(priv->regmap, priv->offset, (u32 *)buff);
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}
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static int pbias_of_to_plat(struct udevice *dev)
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{
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struct pbias_priv *priv = dev_get_priv(dev);
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struct udevice *syscon;
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struct regmap *regmap;
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struct resource res;
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int err;
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err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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"syscon", &syscon);
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if (err) {
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pr_err("%s: unable to find syscon device (%d)\n", __func__,
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err);
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return err;
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}
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regmap = syscon_get_regmap(syscon);
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if (IS_ERR(regmap)) {
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pr_err("%s: unable to find regmap (%ld)\n", __func__,
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PTR_ERR(regmap));
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return PTR_ERR(regmap);
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}
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priv->regmap = regmap;
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err = dev_read_resource(dev, 0, &res);
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if (err) {
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pr_err("%s: unable to find offset (%d)\n", __func__, err);
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return err;
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}
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priv->offset = res.start;
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return 0;
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}
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static int pbias_bind(struct udevice *dev)
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{
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int children;
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children = pmic_bind_children(dev, dev_ofnode(dev),
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pmic_children_info);
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if (!children)
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debug("%s: %s - no child found\n", __func__, dev->name);
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return 0;
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}
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static struct dm_pmic_ops pbias_ops = {
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.read = pbias_read,
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.write = pbias_write,
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};
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static const struct udevice_id pbias_ids[] = {
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{ .compatible = "ti,pbias-dra7" },
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{ .compatible = "ti,pbias-omap2" },
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{ .compatible = "ti,pbias-omap3" },
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{ .compatible = "ti,pbias-omap4" },
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{ .compatible = "ti,pbias-omap5" },
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{ }
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};
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U_BOOT_DRIVER(pbias_pmic) = {
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.name = "pbias_pmic",
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.id = UCLASS_PMIC,
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.of_match = pbias_ids,
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.bind = pbias_bind,
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.ops = &pbias_ops,
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.of_to_plat = pbias_of_to_plat,
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.priv_auto = sizeof(struct pbias_priv),
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};
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static const struct pbias_reg_info pbias_mmc_omap2430 = {
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.enable = BIT(1),
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.enable_mask = BIT(1),
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.vmode = BIT(0),
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.disable_val = 0,
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.enable_time = 100,
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.name = "pbias_mmc_omap2430"
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};
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static const struct pbias_reg_info pbias_sim_omap3 = {
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.enable = BIT(9),
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.enable_mask = BIT(9),
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.vmode = BIT(8),
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.enable_time = 100,
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.name = "pbias_sim_omap3"
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};
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static const struct pbias_reg_info pbias_mmc_omap4 = {
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.enable = BIT(26) | BIT(22),
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.enable_mask = BIT(26) | BIT(25) | BIT(22),
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.disable_val = BIT(25),
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.vmode = BIT(21),
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.enable_time = 100,
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.name = "pbias_mmc_omap4"
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};
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static const struct pbias_reg_info pbias_mmc_omap5 = {
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.enable = BIT(27) | BIT(26),
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.enable_mask = BIT(27) | BIT(25) | BIT(26),
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.disable_val = BIT(25),
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.vmode = BIT(21),
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.enable_time = 100,
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.name = "pbias_mmc_omap5"
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};
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static const struct pbias_reg_info *pbias_reg_infos[] = {
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&pbias_mmc_omap5,
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&pbias_mmc_omap4,
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&pbias_sim_omap3,
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&pbias_mmc_omap2430,
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NULL
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};
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static int pbias_regulator_probe(struct udevice *dev)
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{
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const struct pbias_reg_info **p = pbias_reg_infos;
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struct dm_regulator_uclass_plat *uc_pdata;
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uc_pdata = dev_get_uclass_plat(dev);
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while (*p) {
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int rc;
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rc = dev_read_stringlist_search(dev, "regulator-name",
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(*p)->name);
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if (rc >= 0) {
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debug("found regulator %s\n", (*p)->name);
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break;
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} else if (rc != -ENODATA) {
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return rc;
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}
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p++;
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}
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if (!*p) {
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int i = 0;
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const char *s;
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debug("regulator ");
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while (dev_read_string_index(dev, "regulator-name", i++, &s) >= 0)
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debug("%s'%s' ", (i > 1) ? ", " : "", s);
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debug("%s not supported\n", (i > 2) ? "are" : "is");
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return -EINVAL;
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}
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uc_pdata->type = REGULATOR_TYPE_OTHER;
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dev_set_priv(dev, (void *)*p);
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return 0;
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}
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static int pbias_regulator_get_value(struct udevice *dev)
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{
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const struct pbias_reg_info *p = dev_get_priv(dev);
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int rc;
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u32 reg;
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rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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if (rc)
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return rc;
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debug("%s voltage id %s\n", p->name,
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(reg & p->vmode) ? "3.0v" : "1.8v");
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return (reg & p->vmode) ? 3000000 : 1800000;
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}
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static int pbias_regulator_set_value(struct udevice *dev, int uV)
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{
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const struct pbias_reg_info *p = dev_get_priv(dev);
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int rc, ret;
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u32 reg;
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
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#endif
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rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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if (rc)
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return rc;
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if (uV == 3300000)
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reg |= p->vmode;
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else if (uV == 1800000)
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reg &= ~p->vmode;
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else
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return -EINVAL;
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debug("Setting %s voltage to %s\n", p->name,
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(reg & p->vmode) ? "3.0v" : "1.8v");
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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if (get_cpu_family() == CPU_OMAP36XX) {
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/* Disable extended drain IO before changing PBIAS */
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wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
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writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
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}
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#endif
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ret = pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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if (get_cpu_family() == CPU_OMAP36XX) {
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/* Enable extended drain IO after changing PBIAS */
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writel(wkup_ctrl |
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OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
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OMAP34XX_CTRL_WKUP_CTRL);
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}
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#endif
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return ret;
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}
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static int pbias_regulator_get_enable(struct udevice *dev)
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{
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const struct pbias_reg_info *p = dev_get_priv(dev);
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int rc;
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u32 reg;
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rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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if (rc)
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return rc;
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debug("%s id %s\n", p->name,
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(reg & p->enable_mask) == (p->disable_val) ? "on" : "off");
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return (reg & p->enable_mask) == (p->disable_val);
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}
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static int pbias_regulator_set_enable(struct udevice *dev, bool enable)
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{
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const struct pbias_reg_info *p = dev_get_priv(dev);
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int rc;
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u32 reg;
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
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#endif
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debug("Turning %s %s\n", enable ? "on" : "off", p->name);
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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if (get_cpu_family() == CPU_OMAP36XX) {
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/* Disable extended drain IO before changing PBIAS */
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wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
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writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
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}
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#endif
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rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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if (rc)
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return rc;
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reg &= ~p->enable_mask;
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if (enable)
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reg |= p->enable;
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else
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reg |= p->disable_val;
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rc = pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg));
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#ifdef CONFIG_MMC_OMAP36XX_PINS
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if (get_cpu_family() == CPU_OMAP36XX) {
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/* Enable extended drain IO after changing PBIAS */
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writel(wkup_ctrl |
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OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
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OMAP34XX_CTRL_WKUP_CTRL);
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}
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#endif
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if (rc)
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return rc;
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if (enable)
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udelay(p->enable_time);
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return 0;
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}
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static const struct dm_regulator_ops pbias_regulator_ops = {
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.get_value = pbias_regulator_get_value,
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.set_value = pbias_regulator_set_value,
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.get_enable = pbias_regulator_get_enable,
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.set_enable = pbias_regulator_set_enable,
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};
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U_BOOT_DRIVER(pbias_regulator) = {
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.name = "pbias_regulator",
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.id = UCLASS_REGULATOR,
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.ops = &pbias_regulator_ops,
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.probe = pbias_regulator_probe,
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};
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