mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
7194ab8095
All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111 - cleaned up line lengths - modified all boards that override weak function in this driver - modified all eeprom standalone apps to work with new driver - updated blackfin standalone EEPROM app after testing Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
147 lines
3.2 KiB
C
147 lines
3.2 KiB
C
/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2004
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* BEC Systems <http://bec-systems.com>
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* Cliff Brake <cliff.brake@gmail.com>
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* Support for Accelent/Vibren PXA255 IDP
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <command.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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/* memory and cpu-speed are setup before relocation */
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/* so we do _nothing_ here */
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/* arch number of Lubbock-Board */
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gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa0000100;
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/* turn on serial ports */
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*(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
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/* set PWM for LCD */
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/* a value that works is 60Hz, 77% duty cycle */
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CKEN |= CKEN0_PWM0;
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PWM_CTRL0 = 0x3f;
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PWM_PERVAL0 = 0x3ff;
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PWM_PWDUTY0 = 792;
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/* clear reset to AC97 codec */
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CKEN |= CKEN2_AC97;
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GCR = GCR_COLD_RST;
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/* enable LCD backlight */
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/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
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/* test display */
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/* lcd_puts("This is a test\nTest #2\n"); */
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return 0;
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}
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int board_late_init(void)
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{
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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return 0;
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}
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
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return 0;
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}
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#ifdef DEBUG_BLINKC_ENABLE
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void delay_c(void)
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{
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/* reset OSCR to 0 */
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OSCR = 0;
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while(OSCR > 0x10000)
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;
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while(OSCR < 0xd4000)
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;
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}
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void blink_c(void)
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{
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int led_bit = (1<<10);
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GPDR0 = led_bit;
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GPCR0 = led_bit;
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delay_c();
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GPSR0 = led_bit;
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delay_c();
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GPCR0 = led_bit;
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}
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int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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printf("IDPCMD started\n");
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return 0;
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}
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U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd,
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"custom IDP command",
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"no args at this time"
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);
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#endif
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC91111
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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return rc;
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}
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#endif
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