Tom Rini cbe607b920 Xilinx changes for v2021.04-rc3 ... qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYDUezQAKCRDKSWXLKUoM IbtgAJ9jZ+BOtwFaHR19TENC2DsHTINnnwCfSDn3fU0OFJRI0HD7pRxXr4xrb3M= =Kr8x -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name		2021-02-23 10:45:55 -05:00
..
board.c	Xilinx changes for v2021.04-rc3	2021-02-23 10:45:55 -05:00
board.h	xilinx: board: Read the whole eeprom not just offset	2020-10-27 08:13:32 +01:00
fru.c	xilinx: cmd: Add basic fru format generator	2020-10-27 08:13:32 +01:00
fru.h	fru: common: Record pcie/uuid fields in custom board area	2020-11-20 10:42:54 +01:00
fru_ops.c	fru: ops: avoid out of bounds access	2021-01-05 11:54:53 +01:00
Makefile	xilinx: cmd: Add support for FRU commands	2020-10-27 08:13:32 +01:00