mirror of
https://github.com/AsahiLinux/u-boot
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564637a360
Add the required changes for compiling with DM_ETH on the PPC DPAA platforms. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
307 lines
6.5 KiB
C
307 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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*/
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#include <common.h>
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#include <command.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <image.h>
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#include <init.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include <hwconfig.h>
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#include "../common/sleep.h"
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#include "../common/qixis.h"
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#include "t1040qds.h"
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#include "t1040qds_qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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char buf[64];
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u8 sw;
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struct cpu_type *cpu = gd->arch.cpu;
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static const char *const freq[] = {"100", "125", "156.25", "161.13",
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"122.88", "122.88", "122.88"};
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int clock;
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printf("Board: %sQDS, ", cpu->name);
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
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QIXIS_READ(id), QIXIS_READ(arch));
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x8)
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puts("PromJet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else if (sw == 0x15)
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printf("IFCCard\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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printf("FPGA: v%d (%s), build %d",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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/*
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* Display the actual SERDES reference clocks as configured by the
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* dip switches on the board. Note that the SWx registers could
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* technically be set to force the reference clocks to match the
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* values that the SERDES expects (or vice versa). For now, however,
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* we just display both values and hope the user notices when they
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* don't match.
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*/
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puts("SERDES Reference: ");
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sw = QIXIS_READ(brdcfg[2]);
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clock = (sw >> 6) & 3;
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printf("Clock1=%sMHz ", freq[clock]);
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clock = (sw >> 4) & 3;
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printf("Clock2=%sMHz\n", freq[clock]);
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return 0;
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}
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int select_i2c_ch_pca9547(u8 ch, int bus_num)
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{
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int ret;
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#ifdef CONFIG_DM_I2C
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n", __func__,
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bus_num);
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return ret;
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}
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ret = dm_i2c_write(dev, 0, &ch, 1);
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#else
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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#endif
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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static void qe_board_setup(void)
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{
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u8 brdcfg15, brdcfg9;
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if (hwconfig("qe") && hwconfig("tdm")) {
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brdcfg15 = QIXIS_READ(brdcfg[15]);
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/*
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* TDMRiser uses QE-TDM
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* Route QE_TDM signals to TDM Riser slot
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*/
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QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
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} else if (hwconfig("qe") && hwconfig("uart")) {
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brdcfg15 = QIXIS_READ(brdcfg[15]);
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brdcfg9 = QIXIS_READ(brdcfg[9]);
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/*
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* Route QE_TDM signals to UCC
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* ProfiBus controlled by UCC3
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*/
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brdcfg15 &= 0xfc;
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QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
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QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
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}
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}
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int board_early_init_f(void)
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{
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_SYS_FLASH_BASE
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0F) {
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case QIXIS_SYSCLK_64:
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return 64000000;
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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#define NUM_SRDS_BANKS 2
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int misc_init_r(void)
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{
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u8 sw;
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serdes_corenet_t *srds_regs =
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(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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u32 actual[NUM_SRDS_BANKS] = { 0 };
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int i;
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sw = QIXIS_READ(brdcfg[2]);
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for (i = 0; i < NUM_SRDS_BANKS; i++) {
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unsigned int clock = (sw >> (6 - 2 * i)) & 3;
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switch (clock) {
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case 0:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
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break;
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case 1:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
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break;
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case 2:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
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break;
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}
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}
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puts("SerDes1");
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for (i = 0; i < NUM_SRDS_BANKS; i++) {
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u32 pllcr0 = srds_regs->bank[i].pllcr0;
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u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
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if (expected != actual[i]) {
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printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
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i + 1, serdes_clock_to_string(expected),
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serdes_clock_to_string(actual[i]));
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}
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}
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qe_board_setup();
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = env_get_bootm_low();
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size = env_get_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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#ifdef CONFIG_HAS_FSL_DR_USB
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fsl_fdt_fixup_dr_usb(blob, bd);
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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#ifndef CONFIG_DM_ETH
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fdt_fixup_fman_ethernet(blob);
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#endif
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fdt_fixup_board_enet(blob);
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#endif
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return 0;
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}
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void qixis_dump_switch(void)
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{
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int i, nr_of_cfgsw;
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QIXIS_WRITE(cms[0], 0x00);
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nr_of_cfgsw = QIXIS_READ(cms[1]);
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puts("DIP switch settings dump:\n");
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for (i = 1; i <= nr_of_cfgsw; i++) {
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QIXIS_WRITE(cms[0], i);
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printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
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}
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}
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int board_need_mem_reset(void)
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{
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return 1;
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}
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