mirror of
https://github.com/AsahiLinux/u-boot
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127efc4fe8
This paramter will later be used to initialize OTG ports in host or device mode. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
158 lines
4 KiB
C
158 lines
4 KiB
C
/*
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* Freescale i.MX28 USB Host driver
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <errno.h>
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#include "ehci.h"
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/* This DIGCTL register ungates clock to USB */
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#define HW_DIGCTL_CTRL 0x8001c000
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#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
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#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
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struct ehci_mxs_port {
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uint32_t usb_regs;
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struct mxs_usbphy_regs *phy_regs;
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struct mxs_register_32 *pll;
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uint32_t pll_en_bits;
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uint32_t pll_dis_bits;
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uint32_t gate_bits;
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};
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static const struct ehci_mxs_port mxs_port[] = {
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#ifdef CONFIG_EHCI_MXS_PORT0
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{
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MXS_USBCTRL0_BASE,
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(struct mxs_usbphy_regs *)MXS_USBPHY0_BASE,
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(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
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offsetof(struct mxs_clkctrl_regs,
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hw_clkctrl_pll0ctrl0_reg)),
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CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
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CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
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HW_DIGCTL_CTRL_USB0_CLKGATE,
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},
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#endif
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#ifdef CONFIG_EHCI_MXS_PORT1
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{
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MXS_USBCTRL1_BASE,
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(struct mxs_usbphy_regs *)MXS_USBPHY1_BASE,
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(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
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offsetof(struct mxs_clkctrl_regs,
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hw_clkctrl_pll1ctrl0_reg)),
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CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
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CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
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HW_DIGCTL_CTRL_USB1_CLKGATE,
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},
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#endif
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};
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static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
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{
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struct mxs_register_32 *digctl_ctrl =
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(struct mxs_register_32 *)HW_DIGCTL_CTRL;
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int pll_offset, dig_offset;
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if (enable) {
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pll_offset = offsetof(struct mxs_register_32, reg_set);
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dig_offset = offsetof(struct mxs_register_32, reg_clr);
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writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
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writel(port->pll_en_bits, (u32)port->pll + pll_offset);
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} else {
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pll_offset = offsetof(struct mxs_register_32, reg_clr);
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dig_offset = offsetof(struct mxs_register_32, reg_set);
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writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
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writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
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}
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return 0;
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}
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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int ret;
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uint32_t usb_base, cap_base;
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const struct ehci_mxs_port *port;
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if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
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printf("Invalid port index (index = %d)!\n", index);
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return -EINVAL;
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}
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port = &mxs_port[index];
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/* Reset the PHY block */
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writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
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udelay(10);
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writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
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&port->phy_regs->hw_usbphy_ctrl_clr);
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/* Enable USB clock */
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ret = ehci_mxs_toggle_clock(port, 1);
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if (ret)
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return ret;
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/* Start USB PHY */
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writel(0, &port->phy_regs->hw_usbphy_pwd);
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/* Enable UTMI+ Level 2 and Level 3 compatibility */
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writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
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&port->phy_regs->hw_usbphy_ctrl_set);
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usb_base = port->usb_regs + 0x100;
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*hccr = (struct ehci_hccr *)usb_base;
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cap_base = ehci_readl(&(*hccr)->cr_capbase);
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*hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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int ret;
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uint32_t usb_base, cap_base, tmp;
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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const struct ehci_mxs_port *port;
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if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
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printf("Invalid port index (index = %d)!\n", index);
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return -EINVAL;
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}
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port = &mxs_port[index];
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/* Stop the USB port */
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usb_base = port->usb_regs + 0x100;
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hccr = (struct ehci_hccr *)usb_base;
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cap_base = ehci_readl(&hccr->cr_capbase);
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hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
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tmp = ehci_readl(&hcor->or_usbcmd);
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tmp &= ~CMD_RUN;
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ehci_writel(tmp, &hcor->or_usbcmd);
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/* Disable the PHY */
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tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
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USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
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USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
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USBPHY_PWD_TXPWDFS;
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writel(tmp, &port->phy_regs->hw_usbphy_pwd);
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/* Disable USB clock */
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ret = ehci_mxs_toggle_clock(port, 0);
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return ret;
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}
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