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u-boot/arch/x86/dts/microcode
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Bin Meng 33fb6c0100 x86: ivybridge: Add microcode blobs for all the steppings 
This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-01-13 12:20:15 +08:00
..
m12206a7_00000029.dtsi x86: ivybridge: Update the microcode 2014-12-18 17:26:05 -07:00
m12306a2_00000008.dtsi x86: ivybridge: Add microcode blobs for all the steppings 2016-01-13 12:20:15 +08:00
m12306a4_00000007.dtsi x86: ivybridge: Add microcode blobs for all the steppings 2016-01-13 12:20:15 +08:00
m12306a5_00000007.dtsi x86: ivybridge: Add microcode blobs for all the steppings 2016-01-13 12:20:15 +08:00
m12306a8_00000010.dtsi x86: ivybridge: Add microcode blobs for all the steppings 2016-01-13 12:20:15 +08:00
m12306a9_0000001b.dtsi x86: ivybridge: Update the microcode 2014-12-18 17:26:05 -07:00
m0130673322.dtsi x86: Add support for Intel Minnowboard Max 2015-02-06 12:07:39 -07:00
m0130679901.dtsi x86: baytrail: Add microcode for BayTrail-I D0 stepping 2015-08-26 07:54:09 -07:00
m0220661105_cv.dtsi x86: Integrate Tunnel Creek processor microcode 2014-12-18 17:26:05 -07:00
m0230671117.dtsi x86: Add microcode for BayTrail-I B0 stepping 2015-08-05 08:42:39 -06:00