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Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications Processor Reference Manual and "Figure 18-5. BUS clock generation" of i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk sources from pll4_main_clk(pll_audio), the calculation is wrong. Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support for decode_pll. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> |
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.. | ||
clock.h | ||
crm_regs.h | ||
gpio.h | ||
imx-regs.h | ||
iomux.h | ||
mx6-ddr.h | ||
mx6-pins.h | ||
mx6dl-ddr.h | ||
mx6dl_pins.h | ||
mx6q-ddr.h | ||
mx6q_pins.h | ||
mx6sl-ddr.h | ||
mx6sl_pins.h | ||
mx6sx-ddr.h | ||
mx6sx_pins.h | ||
mx6ul-ddr.h | ||
mx6ul_pins.h | ||
mxc_hdmi.h | ||
sys_proto.h |