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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
6 lines
138 B
C
6 lines
138 B
C
#ifndef _ASM_XTENSA_UNALIGNED_H
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#define _ASM_XTENSA_UNALIGNED_H
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#include <asm-generic/unaligned.h>
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#endif /* _ASM_XTENSA_UNALIGNED_H */
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