mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
842033e696
The pci_indirect.c file is always compiled when CONFIG_PCI is defined although the indirect PCI bridge support is not needed by every board. Introduce a new CONFIG_PCI_INDIRECT_BRIDGE config option and only compile indirect PCI bridge support if this options is enabled. Also add the new option into the configuration files of the boards which needs that. Compile tested for powerpc, x86, arm and nds32. MAKEALL results: powerpc: --------------------- SUMMARY ---------------------------- Boards compiled: 641 Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB ) ---------------------------------------------------------- Note: the warnings for ELPPC and MPC8323ERDB are present even without the actual patch. x86: --------------------- SUMMARY ---------------------------- Boards compiled: 1 ---------------------------------------------------------- arm: --------------------- SUMMARY ---------------------------- Boards compiled: 311 ---------------------------------------------------------- nds32: --------------------- SUMMARY ---------------------------- Boards compiled: 3 ---------------------------------------------------------- Cc: Tom Rini <trini@ti.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
507 lines
14 KiB
C
507 lines
14 KiB
C
/*
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* Copyright (C) Matrix Vision GmbH 2008
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*
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* Matrix Vision mvBlueLYNX-M7 configuration file
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* based on Freescale's MPC8349ITX.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <version.h>
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1
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#define CONFIG_MPC83xx 1
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#define CONFIG_MPC834x 1
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#define CONFIG_MPC8343 1
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define CONFIG_SYS_IMMR 0xE0000000
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#define CONFIG_PCI
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_PCI_SKIP_HOST_BRIDGE
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#define CONFIG_HARD_I2C
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#define CONFIG_TSEC_ENET
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#define CONFIG_MPC8XXX_SPI
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#define CONFIG_HARD_SPI
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#define MVBLM7_MMC_CS 0x04000000
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#define CONFIG_MISC_INIT_R
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/* I2C */
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#define CONFIG_FSL_I2C
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* DDR Setup
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*/
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#undef CONFIG_SPD_EEPROM
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#define CONFIG_SYS_DDR_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_83XX_DDR_USES_CS0 1
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#define CONFIG_SYS_MEMTEST_START (60<<20)
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#define CONFIG_SYS_MEMTEST_END (70<<20)
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \
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| DDRCDR_NZ_HIZ \
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| DDRCDR_Q_DRN)
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/* 0x22000001 */
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_DDR_SIZE 512
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
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#define CONFIG_SYS_DDR_TIMING_0 0x00260802
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#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
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#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_INTERVAL 0x02000100
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#define CONFIG_SYS_DDR_MODE 0x04040242
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#define CONFIG_SYS_DDR_MODE2 0x00800000
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/* Flash */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BASE 0xFF800000
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#define CONFIG_SYS_FLASH_SIZE 8
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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| BR_PS_16 \
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| BR_MS_GPCM \
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| BR_V)
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX_SET \
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| OR_GPCM_EHTR_SET \
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| OR_GPCM_EAD)
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
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/*
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* U-Boot memory configuration
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#undef CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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/*
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* Local Bus LCRR and LBCR regs
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* LCRR: DLL bypass, Clock divider is 4
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_LSRT 0x32000000
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/* LB refresh timer prescal, 266MHz/32*/
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_CONSOLE ttyS0
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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#define MV_DTB_NAME "mvblm7.dtb"
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/*
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* PCI
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCI1_MMIO_BASE \
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(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
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#define CONFIG_NET_RETRY_COUNT 3
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#define CONFIG_PCI_66M
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#define CONFIG_83XX_CLKIN 66666667
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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/* TSEC */
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#define CONFIG_GMII
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#define CONFIG_SYS_VSC8601_SKEWFIX
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#define CONFIG_SYS_VSC8601_SKEW_TX 3
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#define CONFIG_SYS_VSC8601_SKEW_RX 3
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#define CONFIG_TSEC1
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#define CONFIG_TSEC2
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_FEC1_PHY_NORXERR
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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#define TSEC1_PHY_ADDR 0x10
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#define TSEC1_PHYIDX 0
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#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_FEC2_PHY_NORXERR
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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#define TSEC2_PHY_ADDR 0x11
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#define TSEC2_PHYIDX 0
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#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
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#define CONFIG_ETHPRIME "TSEC0"
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#define CONFIG_BOOTP_VENDOREX
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_NTPSERVER
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#define CONFIG_BOOTP_RANDOM_DELAY
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#define CONFIG_BOOTP_SEND_HOSTNAME
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/* USB */
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#define CONFIG_SYS_USB_HOST
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_HAS_FSL_DR_USB
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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/*
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* Environment
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*/
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#undef CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR 0xFF800000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_LOADS_ECHO
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_FPGA
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#define CONFIG_CMD_USB
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#define CONFIG_DOS_PARTITION
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#undef CONFIG_WATCHDOG
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_HUSH_PARSER
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 0x200000
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#define CONFIG_SYS_PROMPT "mvBL-M7> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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/* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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#define CONFIG_SYS_HRCW_LOW 0x0
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#define CONFIG_SYS_HRCW_HIGH 0x0
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/*
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* System performance
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
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#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
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/* clocking */
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#define CONFIG_SYS_SCCR_ENCCM 0
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#define CONFIG_SYS_SCCR_USBMPHCM 0
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#define CONFIG_SYS_SCCR_USBDRCM 2
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#define CONFIG_SYS_SCCR_TSEC1CM 1
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#define CONFIG_SYS_SCCR_TSEC2CM 1
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#define CONFIG_SYS_SICRH 0x1fef0003
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#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
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HID0_ENABLE_INSTRUCTION_CACHE)
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#define CONFIG_SYS_HID2 HID2_HBE
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#define CONFIG_HIGH_BATS 1
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/* DDR */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
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| BATL_PP_RW \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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/* PCI */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
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| BATL_PP_RW \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
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| BATL_PP_RW \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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/* no PCI2 */
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#define CONFIG_SYS_IBAT3L 0
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#define CONFIG_SYS_IBAT3U 0
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#define CONFIG_SYS_IBAT4L 0
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#define CONFIG_SYS_IBAT4U 0
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/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
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| BATL_PP_RW \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
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#define CONFIG_SYS_IBAT6L (0xF0000000 \
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| BATL_PP_RW \
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| BATL_MEMCOHERENCE \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT6U (0xF0000000 \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_IBAT7L 0
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#define CONFIG_SYS_IBAT7U 0
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_NETDEV eth0
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/* Default path and filenames */
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_STOP_STR "s"
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_RESET_TO_RETRY 1000
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#define MV_CI "mvBL-M7"
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#define MV_VCI "mvBL-M7"
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#define MV_FPGA_DATA 0xfff40000
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#define MV_FPGA_SIZE 0
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#define MV_KERNEL_ADDR 0xff810000
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#define MV_INITRD_ADDR 0xffb00000
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#define MV_SCRIPT_ADDR 0xff804000
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#define MV_SCRIPT_ADDR2 0xff806000
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#define MV_DTB_ADDR 0xff808000
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#define MV_INITRD_LENGTH 0x00400000
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#define CONFIG_SHOW_BOOT_PROGRESS 1
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#define MV_KERNEL_ADDR_RAM 0x00100000
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#define MV_DTB_ADDR_RAM 0x00600000
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#define MV_INITRD_ADDR_RAM 0x01000000
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#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
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"then source ${script_addr}; " \
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"else source ${script_addr2}; " \
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"fi;"
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#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"console_nr=0\0" \
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"baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0" \
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"fpga=0\0" \
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"fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
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"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
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"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
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"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
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"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
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"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
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"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
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"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
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"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
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"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
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"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
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"dtb_name=" __stringify(MV_DTB_NAME) "\0" \
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|
"mv_version=" U_BOOT_VERSION "\0" \
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|
"dhcp_client_id=" MV_CI "\0" \
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|
"dhcp_vendor-class-identifier=" MV_VCI "\0" \
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|
"netretry=no\0" \
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|
"use_static_ipaddr=no\0" \
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|
"static_ipaddr=192.168.90.10\0" \
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|
"static_netmask=255.255.255.0\0" \
|
|
"static_gateway=0.0.0.0\0" \
|
|
"initrd_name=uInitrd.mvBL-M7-rfs\0" \
|
|
"zcip=no\0" \
|
|
"netboot=yes\0" \
|
|
"mvtest=Ff\0" \
|
|
"tried_bootfromflash=no\0" \
|
|
"tried_bootfromnet=no\0" \
|
|
"bootfile=mvblm72625.boot\0" \
|
|
"use_dhcp=yes\0" \
|
|
"gev_start=yes\0" \
|
|
"mvbcdma_debug=0\0" \
|
|
"mvbcia_debug=0\0" \
|
|
"propdev_debug=0\0" \
|
|
"gevss_debug=0\0" \
|
|
"watchdog=0\0" \
|
|
"usb_dr_mode=host\0" \
|
|
"sensor_cnt=2\0" \
|
|
""
|
|
|
|
#define CONFIG_FPGA_COUNT 1
|
|
#define CONFIG_FPGA
|
|
#define CONFIG_FPGA_ALTERA
|
|
#define CONFIG_FPGA_CYCLON2
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|
|
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#endif
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