mirror of
https://github.com/AsahiLinux/u-boot
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7676074ac7
This patch adjusts memory map for secure boot headers on LS2080AQDS and LS2080ARDB platforms. Secure boot headers are placed on NOR flash at offset 0x00600000. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
203 lines
6.6 KiB
Text
203 lines
6.6 KiB
Text
Overview
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--------
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The LS2080A Development System (QDS) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS2080A
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and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
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validation and SW development platform for the Freescale LS2080A, LS2088A
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processor series, with a complete debugging environment.
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LS2080A, LS2088A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
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LS2088A SoC overview.
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LS2080AQDS board Overview
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-----------------------
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- SERDES Connections, 16 lanes supporting:
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- PCI Express - 3.0
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- SGMII, SGMII 2.5
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- QSGMII
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- SATA 3.0
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- XAUI
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- XFI
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- DDR Controller
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- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
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chip-selects and two DIMM connectors. Support is up to 2133MT/s.
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- One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
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and two DIMM connectors. Support is up to 1600MT/s.
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-IFC/Local Bus
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- IFC rev. 2.0 implementation supporting Little Endian connection scheme.
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- One in-socket 128 MB NOR flash 16-bit data bus
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- One 512 MB NAND flash with ECC support
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- IFC Test Port
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- PromJet Port
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- FPGA connection
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- USB 3.0
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- Two high speed USB 3.0 ports
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- First USB 3.0 port configured as Host with Type-A connector
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- Second USB 3.0 port configured as OTG with micro-AB connector
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- SDHC: PCIe x1 Right Angle connector for supporting following cards
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- 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
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- 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
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- 4-bit eMMC Card Rev 4.4 (1.8V only)
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- 8-bit eMMC Card Rev 4.5 (1.8V only)
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- SD Card Rev 2.0 and Rev 3.0
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- DSPI: 3 high-speed flash Memory for storage
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- 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 8 MB high-speed flash Memory (up to 104 MHz)
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- 512 MB low-speed flash Memory (up to 40 MHz)
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- QSPI: via NAND/QSPI Card
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- 4 I2C controllers
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- Two SATA onboard connectors
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- UART
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- Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
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0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
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0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
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0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
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0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
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0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
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0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
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Other addresses are either reserved, or not used directly by U-Boot.
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This list should be updated when more addresses are used.
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IFC region map from core's view
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-------------------------------
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During boot i.e. IFC Region #1:-
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0x30000000 - 0x37ffffff : 128MB : NOR flash
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0x38000000 - 0x3BFFFFFF : 64MB : Promjet
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0x3C000000 - 0x40000000 : 64MB : FPGA etc
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After relocate to DDR i.e. IFC Region #2:-
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0x5_1000_0000..0x5_1fff_ffff Memory Hole
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0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
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0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
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0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
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0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
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Booting Options
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---------------
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a) Promjet Boot
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b) NOR boot
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c) NAND boot
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d) SD boot
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e) QSPI boot
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Memory map for NOR boot
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-------------------------
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Image Flash Offset
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RCW+PBI 0x00000000
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Boot firmware (U-Boot) 0x00100000
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Boot firmware Environment 0x00300000
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PPA firmware 0x00400000
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Secure Headers 0x00600000
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DPAA2 MC 0x00A00000
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DPAA2 DPL 0x00D00000
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DPAA2 DPC 0x00E00000
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Kernel.itb 0x01000000
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Environment Variables
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---------------------
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- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
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the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
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- mcmemsize: MC DRAM block size. If this variable is not defined
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the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
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Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
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-------------------------------------------------------------------
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One needs to use appropriate bootargs to boot Linux flavors which do
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not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
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below:
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=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
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earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
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hugepages=16 mem=2048M'
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X-QSGMII-16PORT riser card
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----------------------------
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The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
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interfaces implemented in PCIe form factor board.
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It supports following:
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- Card can operate with up to 4 QSGMII lane simultaneously
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- Card can operate with up to 8 SGMII lane simultaneously
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Supported card configuration
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- CSEL : ON ON ON ON
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- MSEL1 : ON ON ON ON OFF OFF OFF OFF
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- MSEL2 : OFF OFF OFF OFF ON ON ON ON
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To enable this card: modify hwconfig to add "xqsgmii" variable.
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Supported PHY addresses during SGMII:
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#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
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#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
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#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
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#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
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#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
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#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
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#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
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#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
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Mapping DPMACx to PHY during SGMII
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DPMAC1 -> PHY1-P0
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DPMAC2 -> PHY2-P0
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DPMAC3 -> PHY3-P0
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DPMAC4 -> PHY4-P0
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DPMAC5 -> PHY3-P2
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DPMAC6 -> PHY1-P2
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DPMAC7 -> PHY4-P1
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DPMAC8 -> PHY2-P2
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DPMAC9 -> PHY1-P0
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DPMAC10 -> PHY2-P0
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DPMAC11 -> PHY3-P0
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DPMAC12 -> PHY4-P0
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DPMAC13 -> PHY3-P2
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DPMAC14 -> PHY1-P2
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DPMAC15 -> PHY4-P1
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DPMAC16 -> PHY2-P2
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Supported PHY address during QSGMII
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#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
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#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
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#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
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#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
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#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
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#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
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#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
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#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
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#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
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#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
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#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
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#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
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#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
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#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
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#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
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#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
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Mapping DPMACx to PHY during QSGMII
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DPMAC1 -> PHY1-P3
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DPMAC2 -> PHY1-P2
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DPMAC3 -> PHY1-P1
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DPMAC4 -> PHY1-P0
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DPMAC5 -> PHY2-P3
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DPMAC6 -> PHY2-P2
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DPMAC7 -> PHY2-P1
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DPMAC8 -> PHY2-P0
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DPMAC9 -> PHY3-P0
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DPMAC10 -> PHY3-P1
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DPMAC11 -> PHY3-P2
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DPMAC12 -> PHY3-P3
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DPMAC13 -> PHY4-P0
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DPMAC14 -> PHY4-P1
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DPMAC15 -> PHY4-P2
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DPMAC16 -> PHY4-P3
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