mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
d9a70368db
The <common.h> includes too many headers. Actually, these files
needed to include it for udelay() declaration. Now we can replace
it with <linux/delay.h> thanks to commit 5bc516ed66 ("delay:
collect {m, n, u}delay declarations to include/linux/delay.h").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
110 lines
2.7 KiB
C
110 lines
2.7 KiB
C
/*
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* Copyright (C) 2013-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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#include "../sg-regs.h"
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#include "pll.h"
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static void vpll_init(void)
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{
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u32 tmp, clk_mode_axosel;
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/* Set VPLL27A & VPLL27B */
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tmp = readl(SG_PINMON0);
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clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
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/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
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return;
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/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
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tmp = readl(SC_VPLL27ACTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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/* Unset VPLA_K_LD and VPLB_K_LD bit */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* Set VPLA_M and VPLB_M to 0x20 */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27BCTRL2);
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
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/* Set VPLA_K and VPLB_K for AXO: 25MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066666;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066666;
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writel(tmp, SC_VPLL27BCTRL3);
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} else {
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/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27BCTRL3);
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}
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/* wait 1 usec */
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udelay(1);
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/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* Unset VPLA_SNRST and VPLB_SNRST bit */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL2);
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/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
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tmp = readl(SC_VPLL27ACTRL);
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tmp &= ~0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp &= ~0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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}
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void uniphier_pro4_pll_init(void)
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{
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vpll_init();
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uniphier_ld4_dpll_ssc_en();
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}
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