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Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
161 lines
4.3 KiB
C
161 lines
4.3 KiB
C
/*
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* Freescale i.MX28 APBH DMA
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DMA_H__
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#define __DMA_H__
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#include <linux/list.h>
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#include <linux/compiler.h>
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#define DMA_PIO_WORDS 15
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#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
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/*
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* MXS DMA channels
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*/
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#if defined(CONFIG_MX23)
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enum {
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MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
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MXS_DMA_CHANNEL_AHB_APBH_SSP0,
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MXS_DMA_CHANNEL_AHB_APBH_SSP1,
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MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
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MXS_MAX_DMA_CHANNELS,
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};
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#elif defined(CONFIG_MX28)
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enum {
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MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
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MXS_DMA_CHANNEL_AHB_APBH_SSP1,
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MXS_DMA_CHANNEL_AHB_APBH_SSP2,
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MXS_DMA_CHANNEL_AHB_APBH_SSP3,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
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MXS_DMA_CHANNEL_AHB_APBH_HSADC,
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MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
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MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
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MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
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MXS_MAX_DMA_CHANNELS,
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};
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#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
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enum {
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MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
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MXS_MAX_DMA_CHANNELS,
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};
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#endif
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/*
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* MXS DMA hardware command.
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*
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* This structure describes the in-memory layout of an entire DMA command,
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* including space for the maximum number of PIO accesses. See the appropriate
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* reference manual for a detailed description of what these fields mean to the
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* DMA hardware.
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*/
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#define MXS_DMA_DESC_COMMAND_MASK 0x3
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#define MXS_DMA_DESC_COMMAND_OFFSET 0
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#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
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#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
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#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
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#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
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#define MXS_DMA_DESC_CHAIN (1 << 2)
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#define MXS_DMA_DESC_IRQ (1 << 3)
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#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
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#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
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#define MXS_DMA_DESC_DEC_SEM (1 << 6)
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#define MXS_DMA_DESC_WAIT4END (1 << 7)
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#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
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#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
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#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
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#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
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#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
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#define MXS_DMA_DESC_BYTES_OFFSET 16
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struct mxs_dma_cmd {
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unsigned long next;
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unsigned long data;
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union {
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dma_addr_t address;
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unsigned long alternate;
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};
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unsigned long pio_words[DMA_PIO_WORDS];
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};
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/*
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* MXS DMA command descriptor.
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*
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* This structure incorporates an MXS DMA hardware command structure, along
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* with metadata.
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*/
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#define MXS_DMA_DESC_FIRST (1 << 0)
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#define MXS_DMA_DESC_LAST (1 << 1)
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#define MXS_DMA_DESC_READY (1 << 31)
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struct mxs_dma_desc {
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struct mxs_dma_cmd cmd;
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unsigned int flags;
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dma_addr_t address;
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void *buffer;
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struct list_head node;
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} __aligned(MXS_DMA_ALIGNMENT);
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/**
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* MXS DMA channel
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*
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* This structure represents a single DMA channel. The MXS platform code
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* maintains an array of these structures to represent every DMA channel in the
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* system (see mxs_dma_channels).
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*/
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#define MXS_DMA_FLAGS_IDLE 0
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#define MXS_DMA_FLAGS_BUSY (1 << 0)
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#define MXS_DMA_FLAGS_FREE 0
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#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
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#define MXS_DMA_FLAGS_VALID (1 << 31)
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struct mxs_dma_chan {
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const char *name;
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unsigned long dev;
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struct mxs_dma_device *dma;
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unsigned int flags;
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unsigned int active_num;
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unsigned int pending_num;
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struct list_head active;
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struct list_head done;
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};
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struct mxs_dma_desc *mxs_dma_desc_alloc(void);
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void mxs_dma_desc_free(struct mxs_dma_desc *);
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int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
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int mxs_dma_go(int chan);
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void mxs_dma_init(void);
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int mxs_dma_init_channel(int chan);
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int mxs_dma_release(int chan);
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void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
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#endif /* __DMA_H__ */
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