mirror of
https://github.com/AsahiLinux/u-boot
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76316a318d
timer support interrupt controller support flash support ethernet support cache support board information support env support booting image support adding support for Xilinx ML401
56 lines
1.8 KiB
C
56 lines
1.8 KiB
C
/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* DDR SDRAM */
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#define CONFIG_XILINX_ERAM_START 0x10000000
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#define CONFIG_XILINX_ERAM_SIZE 0x04000000
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/* FLASH_MEMORY Settings */
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#define CONFIG_XILINX_FLASH_START 0x28000000
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#define CONFIG_XILINX_FLASH_SIZE 0x00800000
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/* serial line */
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#define CONFIG_XILINX_UARTLITE_0_BASEADDR 0xA0000000
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#define CONFIG_XILINX_UARTLITE_0_BAUDRATE 115200
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/* GPIO */
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#define CONFIG_XILINX_GPIO_0_BASEADDR 0x90000000
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/* INTC */
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#define CONFIG_XILINX_INTC_0_BASEADDR 0xD1000FC0
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#define CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 12
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/* TIMER */
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#define CONFIG_XILINX_TIMER_0_BASEADDR 0xA2000000
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#define CONFIG_XILINX_TIMER_0_IRQ 0
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/* ethernet */
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#define XPAR_XEMAC_NUM_INSTANCES 1
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#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
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#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
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#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
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#define XPAR_EMAC_0_DEVICE_ID 0
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#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
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#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
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#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
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