mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-03 18:10:13 +00:00
856b30dae5
This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
85 lines
1.6 KiB
C
85 lines
1.6 KiB
C
/*
|
|
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/arch/reset_manager.h>
|
|
#include <asm/io.h>
|
|
|
|
#include <usb.h>
|
|
#include <usb/s3c_udc.h>
|
|
#include <usb_mass_storage.h>
|
|
|
|
#include <micrel.h>
|
|
#include <netdev.h>
|
|
#include <phy.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
void s_init(void) {}
|
|
|
|
/*
|
|
* Miscellaneous platform dependent initialisations
|
|
*/
|
|
int board_init(void)
|
|
{
|
|
/* Address of boot parameters for ATAG (if ATAG is used) */
|
|
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* PHY configuration
|
|
*/
|
|
#ifdef CONFIG_PHY_MICREL_KSZ9021
|
|
int board_phy_config(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
/*
|
|
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
|
|
* to work reliably on most flavors of cyclone5 boards.
|
|
*/
|
|
ret = ksz9021_phy_extended_write(phydev,
|
|
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
|
|
0x0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ksz9021_phy_extended_write(phydev,
|
|
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
|
|
0x0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ksz9021_phy_extended_write(phydev,
|
|
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
|
|
0xf0f0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (phydev->drv->config)
|
|
return phydev->drv->config(phydev);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_GADGET
|
|
struct s3c_plat_otg_data socfpga_otg_data = {
|
|
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
|
|
.usb_gusbcfg = 0x1417,
|
|
};
|
|
|
|
int board_usb_init(int index, enum usb_init_type init)
|
|
{
|
|
return s3c_udc_probe(&socfpga_otg_data);
|
|
}
|
|
|
|
int g_dnl_board_usb_cable_connected(void)
|
|
{
|
|
return 1;
|
|
}
|
|
#endif
|