mirror of
https://github.com/AsahiLinux/u-boot
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424 lines
10 KiB
C
424 lines
10 KiB
C
/*
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* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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enum pll_clocks {
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PLL_SYS, /* System PLL */
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PLL_BUS, /* System Bus PLL*/
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PLL_USBOTG, /* OTG USB PLL */
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PLL_ENET, /* ENET PLL */
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};
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struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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void enable_usboh3_clk(unsigned char enable)
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{
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u32 reg;
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reg = __raw_readl(&imx_ccm->CCGR6);
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if (enable)
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reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
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else
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reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
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__raw_writel(reg, &imx_ccm->CCGR6);
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}
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#ifdef CONFIG_I2C_MXC
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/* i2c_num can be from 0 - 2 */
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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{
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u32 reg;
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u32 mask;
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if (i2c_num > 2)
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return -EINVAL;
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mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1);
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reg = __raw_readl(&imx_ccm->CCGR2);
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if (enable)
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reg |= mask;
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else
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reg &= ~mask;
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__raw_writel(reg, &imx_ccm->CCGR2);
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return 0;
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}
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#endif
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static u32 decode_pll(enum pll_clocks pll, u32 infreq)
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{
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u32 div;
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switch (pll) {
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case PLL_SYS:
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div = __raw_readl(&imx_ccm->analog_pll_sys);
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div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
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return infreq * (div >> 1);
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case PLL_BUS:
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div = __raw_readl(&imx_ccm->analog_pll_528);
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div &= BM_ANADIG_PLL_528_DIV_SELECT;
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return infreq * (20 + (div << 1));
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case PLL_USBOTG:
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div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
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div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
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return infreq * (20 + (div << 1));
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case PLL_ENET:
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div = __raw_readl(&imx_ccm->analog_pll_enet);
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div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
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return (div == 3 ? 125000000 : 25000000 * (div << 1));
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default:
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return 0;
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}
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/* NOTREACHED */
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}
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static u32 get_mcu_main_clk(void)
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{
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u32 reg, freq;
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reg = __raw_readl(&imx_ccm->cacrr);
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reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
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reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
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freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
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return freq / (reg + 1);
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}
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u32 get_periph_clk(void)
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{
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u32 reg, freq = 0;
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reg = __raw_readl(&imx_ccm->cbcdr);
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if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
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reg = __raw_readl(&imx_ccm->cbcmr);
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reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
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reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
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switch (reg) {
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case 0:
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freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
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break;
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case 1:
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case 2:
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freq = CONFIG_SYS_MX6_HCLK;
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break;
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default:
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break;
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}
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} else {
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reg = __raw_readl(&imx_ccm->cbcmr);
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reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
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reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
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switch (reg) {
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case 0:
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freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
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break;
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case 1:
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freq = PLL2_PFD2_FREQ;
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break;
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case 2:
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freq = PLL2_PFD0_FREQ;
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break;
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case 3:
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freq = PLL2_PFD2_DIV_FREQ;
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break;
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default:
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break;
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}
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}
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return freq;
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}
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static u32 get_ipg_clk(void)
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{
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u32 reg, ipg_podf;
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reg = __raw_readl(&imx_ccm->cbcdr);
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reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
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ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
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return get_ahb_clk() / (ipg_podf + 1);
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}
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static u32 get_ipg_per_clk(void)
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{
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u32 reg, perclk_podf;
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reg = __raw_readl(&imx_ccm->cscmr1);
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perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
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return get_ipg_clk() / (perclk_podf + 1);
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}
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static u32 get_uart_clk(void)
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{
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u32 reg, uart_podf;
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reg = __raw_readl(&imx_ccm->cscdr1);
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reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
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uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
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return PLL3_80M / (uart_podf + 1);
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}
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static u32 get_cspi_clk(void)
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{
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u32 reg, cspi_podf;
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reg = __raw_readl(&imx_ccm->cscdr2);
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reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
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cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
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return PLL3_60M / (cspi_podf + 1);
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}
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static u32 get_axi_clk(void)
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{
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u32 root_freq, axi_podf;
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u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
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axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
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axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
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if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
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if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
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root_freq = PLL2_PFD2_FREQ;
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else
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root_freq = PLL3_PFD1_FREQ;
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} else
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root_freq = get_periph_clk();
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return root_freq / (axi_podf + 1);
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}
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static u32 get_emi_slow_clk(void)
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{
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u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
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cscmr1 = __raw_readl(&imx_ccm->cscmr1);
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emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
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emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
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emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
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emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
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switch (emi_clk_sel) {
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case 0:
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root_freq = get_axi_clk();
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break;
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case 1:
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root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
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break;
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case 2:
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root_freq = PLL2_PFD2_FREQ;
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break;
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case 3:
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root_freq = PLL2_PFD0_FREQ;
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break;
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}
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return root_freq / (emi_slow_pof + 1);
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}
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static u32 get_mmdc_ch0_clk(void)
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{
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u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
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u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
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MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
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return get_periph_clk() / (mmdc_ch0_podf + 1);
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}
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static u32 get_usdhc_clk(u32 port)
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{
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u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
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u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
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u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
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switch (port) {
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case 0:
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usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
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MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
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clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
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break;
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case 1:
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usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
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MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
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clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
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break;
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case 2:
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usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
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MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
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clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
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break;
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case 3:
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usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
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MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
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clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
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break;
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default:
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break;
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}
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if (clk_sel)
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root_freq = PLL2_PFD0_FREQ;
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else
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root_freq = PLL2_PFD2_FREQ;
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return root_freq / (usdhc_podf + 1);
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}
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u32 imx_get_uartclk(void)
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{
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return get_uart_clk();
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}
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u32 imx_get_fecclk(void)
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{
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return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
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}
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int enable_sata_clock(void)
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{
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u32 reg = 0;
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s32 timeout = 100000;
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struct mxc_ccm_reg *const imx_ccm
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= (struct mxc_ccm_reg *) CCM_BASE_ADDR;
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/* Enable sata clock */
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reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
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reg |= MXC_CCM_CCGR5_CG2_MASK;
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writel(reg, &imx_ccm->CCGR5);
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/* Enable PLLs */
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reg = readl(&imx_ccm->analog_pll_enet);
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reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
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writel(reg, &imx_ccm->analog_pll_enet);
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reg |= BM_ANADIG_PLL_SYS_ENABLE;
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while (timeout--) {
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if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
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break;
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}
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if (timeout <= 0)
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return -EIO;
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reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
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writel(reg, &imx_ccm->analog_pll_enet);
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reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
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writel(reg, &imx_ccm->analog_pll_enet);
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return 0 ;
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return get_mcu_main_clk();
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case MXC_PER_CLK:
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return get_periph_clk();
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case MXC_AHB_CLK:
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return get_ahb_clk();
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case MXC_IPG_CLK:
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return get_ipg_clk();
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case MXC_IPG_PERCLK:
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return get_ipg_per_clk();
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case MXC_UART_CLK:
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return get_uart_clk();
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case MXC_CSPI_CLK:
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return get_cspi_clk();
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case MXC_AXI_CLK:
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return get_axi_clk();
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case MXC_EMI_SLOW_CLK:
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return get_emi_slow_clk();
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case MXC_DDR_CLK:
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return get_mmdc_ch0_clk();
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case MXC_ESDHC_CLK:
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return get_usdhc_clk(0);
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case MXC_ESDHC2_CLK:
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return get_usdhc_clk(1);
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case MXC_ESDHC3_CLK:
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return get_usdhc_clk(2);
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case MXC_ESDHC4_CLK:
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return get_usdhc_clk(3);
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case MXC_SATA_CLK:
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return get_ahb_clk();
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default:
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break;
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}
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return -1;
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}
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/*
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* Dump some core clockes.
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*/
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int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 freq;
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freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
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printf("PLL_SYS %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
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printf("PLL_BUS %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
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printf("PLL_OTG %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
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printf("PLL_NET %8d MHz\n", freq / 1000000);
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printf("\n");
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printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
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printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
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printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
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printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
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printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
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printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
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printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
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printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
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printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
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printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
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printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
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printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
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return 0;
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}
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/***************************************************/
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
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"display clocks",
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""
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);
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