u-boot/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
Masahiro Yamada 3365b4eb55 ARM: UniPhier: add PH1-sLD3 SoC support
The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-07-23 23:42:22 +09:00

37 lines
1 KiB
C

/*
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
/* only address/data multiplex mode is supported */
/* XECS0 : boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02);
/* XECS1 : sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
/* XECS2 : peripherals */
writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20);
writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21);
writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE2);
sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
}