mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-26 22:52:18 +00:00
1163625898
The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
147 lines
4.7 KiB
Text
147 lines
4.7 KiB
Text
#
|
|
# Multifunction miscellaneous devices
|
|
#
|
|
|
|
menu "Multifunction device drivers"
|
|
|
|
config MISC
|
|
bool "Enable Driver Model for Misc drivers"
|
|
depends on DM
|
|
help
|
|
Enable driver model for miscellaneous devices. This class is
|
|
used only for those do not fit other more general classes. A
|
|
set of generic read, write and ioctl methods may be used to
|
|
access the device.
|
|
|
|
config ALTERA_SYSID
|
|
bool "Altera Sysid support"
|
|
depends on MISC
|
|
help
|
|
Select this to enable a sysid for Altera devices. Please find
|
|
details on the "Embedded Peripherals IP User Guide" of Altera.
|
|
|
|
config CMD_CROS_EC
|
|
bool "Enable crosec command"
|
|
depends on CROS_EC
|
|
help
|
|
Enable command-line access to the Chrome OS EC (Embedded
|
|
Controller). This provides the 'crosec' command which has
|
|
a number of sub-commands for performing EC tasks such as
|
|
updating its flash, accessing a small saved context area
|
|
and talking to the I2C bus behind the EC (if there is one).
|
|
|
|
config CROS_EC
|
|
bool "Enable Chrome OS EC"
|
|
help
|
|
Enable access to the Chrome OS EC. This is a separate
|
|
microcontroller typically available on a SPI bus on Chromebooks. It
|
|
provides access to the keyboard, some internal storage and may
|
|
control access to the battery and main PMIC depending on the
|
|
device. You can use the 'crosec' command to access it.
|
|
|
|
config CROS_EC_I2C
|
|
bool "Enable Chrome OS EC I2C driver"
|
|
depends on CROS_EC
|
|
help
|
|
Enable I2C access to the Chrome OS EC. This is used on older
|
|
ARM Chromebooks such as snow and spring before the standard bus
|
|
changed to SPI. The EC will accept commands across the I2C using
|
|
a special message protocol, and provide responses.
|
|
|
|
config CROS_EC_LPC
|
|
bool "Enable Chrome OS EC LPC driver"
|
|
depends on CROS_EC
|
|
help
|
|
Enable I2C access to the Chrome OS EC. This is used on x86
|
|
Chromebooks such as link and falco. The keyboard is provided
|
|
through a legacy port interface, so on x86 machines the main
|
|
function of the EC is power and thermal management.
|
|
|
|
config CROS_EC_SANDBOX
|
|
bool "Enable Chrome OS EC sandbox driver"
|
|
depends on CROS_EC && SANDBOX
|
|
help
|
|
Enable a sandbox emulation of the Chrome OS EC. This supports
|
|
keyboard (use the -l flag to enable the LCD), verified boot context,
|
|
EC flash read/write/erase support and a few other things. It is
|
|
enough to perform a Chrome OS verified boot on sandbox.
|
|
|
|
config CROS_EC_SPI
|
|
bool "Enable Chrome OS EC SPI driver"
|
|
depends on CROS_EC
|
|
help
|
|
Enable SPI access to the Chrome OS EC. This is used on newer
|
|
ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
|
|
provides a faster and more robust interface than I2C but the bugs
|
|
are less interesting.
|
|
|
|
config FSL_SEC_MON
|
|
bool "Enable FSL SEC_MON Driver"
|
|
help
|
|
Freescale Security Monitor block is responsible for monitoring
|
|
system states.
|
|
Security Monitor can be transitioned on any security failures,
|
|
like software violations or hardware security violations.
|
|
|
|
config MXC_OCOTP
|
|
bool "Enable MXC OCOTP Driver"
|
|
help
|
|
If you say Y here, you will get support for the One Time
|
|
Programmable memory pages that are stored on the some
|
|
Freescale i.MX processors.
|
|
|
|
config PWRSEQ
|
|
bool "Enable power-sequencing drivers"
|
|
depends on DM
|
|
help
|
|
Power-sequencing drivers provide support for controlling power for
|
|
devices. They are typically referenced by a phandle from another
|
|
device. When the device is started up, its power sequence can be
|
|
initiated.
|
|
|
|
config SPL_PWRSEQ
|
|
bool "Enable power-sequencing drivers for SPL"
|
|
depends on PWRSEQ
|
|
help
|
|
Power-sequencing drivers provide support for controlling power for
|
|
devices. They are typically referenced by a phandle from another
|
|
device. When the device is started up, its power sequence can be
|
|
initiated.
|
|
|
|
config PCA9551_LED
|
|
bool "Enable PCA9551 LED driver"
|
|
help
|
|
Enable driver for PCA9551 LED controller. This controller
|
|
is connected via I2C. So I2C needs to be enabled.
|
|
|
|
config PCA9551_I2C_ADDR
|
|
hex "I2C address of PCA9551 LED controller"
|
|
depends on PCA9551_LED
|
|
default 0x60
|
|
help
|
|
The I2C address of the PCA9551 LED controller.
|
|
|
|
config SYSRESET
|
|
bool "Enable support for system reset drivers"
|
|
depends on DM
|
|
help
|
|
Enable system reset drivers which can be used to reset the CPU or
|
|
board. Each driver can provide a reset method which will be called
|
|
to effect a reset. The uclass will try all available drivers when
|
|
reset_walk() is called.
|
|
|
|
config WINBOND_W83627
|
|
bool "Enable Winbond Super I/O driver"
|
|
help
|
|
If you say Y here, you will get support for the Winbond
|
|
W83627 Super I/O driver. This can be used to enable the
|
|
legacy UART or other devices in the Winbond Super IO chips
|
|
on X86 platforms.
|
|
|
|
config QFW
|
|
bool
|
|
help
|
|
Hidden option to enable QEMU fw_cfg interface. This will be selected by
|
|
either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
|
|
|
|
endmenu
|