mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 10:30:32 +00:00
90496afc27
Allows to change clock frequency of debug uart, thus supporting wide range of baudrates. Enable / disable functionality is not implemented yet. In most use cases of SDM845 (i.e. mobile phones and tablets) it's not needed, because qualcomm first stage bootloader leaves it initialized, and on the other hand there's no possibility to replace signed first stage bootloader with u-boot. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Tom Rini <trini@konsulko.com>
92 lines
2.2 KiB
C
92 lines
2.2 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Clock drivers for Qualcomm SDM845
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*
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* (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
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* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
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*
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* Based on Little Kernel driver, simplified
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-snapdragon.h"
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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struct freq_tbl {
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uint freq;
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uint src;
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u8 pre_div;
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u16 m;
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u16 n;
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};
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static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
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F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
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F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
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F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
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F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
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F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
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F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
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F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
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F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
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F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
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F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
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F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
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F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
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F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
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F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
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F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
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{ }
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};
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static const struct bcr_regs uart2_regs = {
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.cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
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.cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
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.M = SE9_UART_APPS_M,
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.N = SE9_UART_APPS_N,
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.D = SE9_UART_APPS_D,
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};
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const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
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{
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if (!f)
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return NULL;
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if (!f->freq)
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return f;
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for (; f->freq; f++)
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if (rate <= f->freq)
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return f;
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/* Default to our fastest rate */
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return f - 1;
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}
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static int clk_init_uart(struct msm_clk_priv *priv, uint rate)
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{
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const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
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clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
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freq->pre_div, freq->m, freq->n, freq->src);
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return 0;
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}
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ulong msm_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case 0x58: /*UART2*/
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return clk_init_uart(priv, rate);
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default:
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return 0;
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}
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}
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