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bdaa976153
Fix these spelling errors the header file and documentation. Fix a small typo in the PCI documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
171 lines
5.9 KiB
ReStructuredText
171 lines
5.9 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+
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PCI with Driver Model
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=====================
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How busses are scanned
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----------------------
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Any config read will end up at pci_read_config(). This uses
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uclass_get_device_by_seq() to get the PCI bus for a particular bus number.
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Bus number 0 will need to be requested first, and the alias in the device
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tree file will point to the correct device::
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aliases {
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pci0 = &pci;
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};
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pci: pci-controller {
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compatible = "sandbox,pci";
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...
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};
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If there is no alias the devices will be numbered sequentially in the device
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tree.
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The call to uclass_get_device() will cause the PCI bus to be probed.
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This does a scan of the bus to locate available devices. These devices are
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bound to their appropriate driver if available. If there is no driver, then
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they are bound to a generic PCI driver which does nothing.
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After probing a bus, the available devices will appear in the device tree
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under that bus.
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Note that this is all done on a lazy basis, as needed, so until something is
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touched on PCI (eg: a call to pci_find_devices()) it will not be probed.
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PCI devices can appear in the flattened device tree. If they do, their node
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often contains extra information which cannot be derived from the PCI IDs or
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PCI class of the device. Each PCI device node must have a <reg> property, as
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defined by the IEEE Std 1275-1994 PCI bus binding document v2.1. Compatible
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string list is optional and generally not needed, since PCI is discoverable
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bus, albeit there are justified exceptions. If the compatible string is
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present, matching on it takes precedence over PCI IDs and PCI classes.
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Note we must describe PCI devices with the same bus hierarchy as the
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hardware, otherwise driver model cannot detect the correct parent/children
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relationship during PCI bus enumeration thus PCI devices won't be bound to
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their drivers accordingly. A working example like below::
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pci {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "pci-x86";
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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pcie@17,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "pci-bridge";
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u-boot,dm-pre-reloc;
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reg = <0x0000b800 0x0 0x0 0x0 0x0>;
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topcliff@0,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "pci-bridge";
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u-boot,dm-pre-reloc;
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reg = <0x00010000 0x0 0x0 0x0 0x0>;
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pciuart0: uart@a,1 {
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compatible = "pci8086,8811.00",
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"pci8086,8811",
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"pciclass,070002",
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"pciclass,0700",
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"x86-uart";
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u-boot,dm-pre-reloc;
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reg = <0x00025100 0x0 0x0 0x0 0x0
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0x01025110 0x0 0x0 0x0 0x0>;
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......
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};
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......
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};
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};
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......
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};
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In this example, the root PCI bus node is the "/pci" which matches "pci-x86"
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driver. It has a subnode "pcie@17,0" with driver "pci-bridge". "pcie@17,0"
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also has subnode "topcliff@0,0" which is a "pci-bridge" too. Under that bridge,
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a PCI UART device "uart@a,1" is described. This exactly reflects the hardware
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bus hierarchy: on the root PCI bus, there is a PCIe root port which connects
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to a downstream device Topcliff chipset. Inside Topcliff chipset, it has a
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PCIe-to-PCI bridge and all the chipset integrated devices like the PCI UART
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device are on the PCI bus. Like other devices in the device tree, if we want
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to bind PCI devices before relocation, "u-boot,dm-pre-reloc" must be declared
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in each of these nodes.
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If PCI devices are not listed in the device tree, U_BOOT_PCI_DEVICE can be used
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to specify the driver to use for the device. The device tree takes precedence
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over U_BOOT_PCI_DEVICE. Please note with U_BOOT_PCI_DEVICE, only drivers with
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DM_FLAG_PRE_RELOC will be bound before relocation. If neither device tree nor
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U_BOOT_PCI_DEVICE is provided, the built-in driver (either pci_bridge_drv or
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pci_generic_drv) will be used.
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Sandbox
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-------
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With sandbox we need a device emulator for each device on the bus since there
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is no real PCI bus. This works by looking in the device tree node for an
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emulator driver. For example::
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pci@1f,0 {
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compatible = "pci-generic";
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reg = <0xf800 0 0 0 0>;
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sandbox,emul = <&emul_1f>;
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};
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pci-emul {
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compatible = "sandbox,pci-emul-parent";
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emul_1f: emul@1f,0 {
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compatible = "sandbox,swap-case";
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};
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};
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This means that there is a 'sandbox,swap-case' driver at that bus position.
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Note that the first cell in the 'reg' value is the bus/device/function. See
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PCI_BDF() for the encoding (it is also specified in the IEEE Std 1275-1994
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PCI bus binding document, v2.1)
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The pci-emul node should go outside the pci bus node, since otherwise it will
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be scanned as a PCI device, causing confusion.
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When this bus is scanned we will end up with something like this::
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`- * pci-controller @ 05c660c8, 0
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`- pci@1f,0 @ 05c661c8, 63488
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`- emul@1f,0 @ 05c662c8
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When accesses go to the pci@1f,0 device they are forwarded to its emulator.
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The sandbox PCI drivers also support dynamic driver binding, allowing device
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driver to declare the driver binding information via U_BOOT_PCI_DEVICE(),
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eliminating the need to provide any device tree node under the host controller
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node. It is required a "sandbox,dev-info" property must be provided in the
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host controller node for this functionality to work.
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.. code-block:: none
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pci1: pci-controller1 {
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compatible = "sandbox,pci";
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...
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sandbox,dev-info = <0x08 0x00 0x1234 0x5678
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0x0c 0x00 0x1234 0x5678>;
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};
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The "sandbox,dev-info" property specifies all dynamic PCI devices on this bus.
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Each dynamic PCI device is encoded as 4 cells a group. The first and second
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cells are PCI device number and function number respectively. The third and
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fourth cells are PCI vendor ID and device ID respectively.
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When this bus is scanned we will end up with something like this::
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pci [ + ] pci_sandbo |-- pci-controller1
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pci_emul [ ] sandbox_sw | |-- sandbox_swap_case_emul
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pci_emul [ ] sandbox_sw | `-- sandbox_swap_case_emul
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