u-boot/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
Tim Harvey 22adeef0f2 arm: dts: imx8mp-venice-gw74xx: update M2 gpio hogs
Update the M2 socket gpio hogs such that they are not active on boot by
flagging them as GPIO_ACTIVE_HIGH so that 'output-high' drives high.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-10-20 17:35:52 +02:00

244 lines
3.3 KiB
Text

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Gateworks Corporation
*/
#include "imx8mp-u-boot.dtsi"
/ {
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
wdt-reboot {
compatible = "wdt-reboot";
u-boot,dm-spl;
wdt = <&wdog1>;
};
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&ethphy0 {
reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
reset-post-delay-us = <300000>;
};
&fec {
phy-reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};
&gpio1 {
u-boot,dm-spl;
dio0_hog {
gpio-hog;
input;
gpios = <9 GPIO_ACTIVE_LOW>;
line-name = "dio0";
};
dio1_hog {
gpio-hog;
input;
gpios = <11 GPIO_ACTIVE_LOW>;
line-name = "dio1";
};
};
&gpio2 {
u-boot,dm-spl;
pcie1_wdis_hog {
gpio-hog;
gpios = <17 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "pcie1_wdis#";
};
pcie2_wdis_hog {
gpio-hog;
gpios = <18 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "pcie2_wdis#";
};
pcie3_wdis_hog {
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "pcie3_wdis#";
};
};
&gpio3 {
u-boot,dm-spl;
m2_dis2_hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_gdis#";
};
m2rst_hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_rst#";
};
m2_off_hog {
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_off#";
};
};
&gpio4 {
u-boot,dm-spl;
m2_dis1_hog {
gpio-hog;
gpios = <18 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "m2_wdis#";
};
rs485_en {
gpio-hog;
gpios = <31 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "rs485_en";
};
};
&gpio5 {
u-boot,dm-spl;
rs485_half {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "rs485_hd";
};
rs485_term {
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "rs485_term";
};
};
&i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&i2c3 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
lan1: port@0 {
phy-handle = <&sw_phy0>;
};
lan2: port@1 {
phy-handle = <&sw_phy1>;
};
lan3: port@2 {
phy-handle = <&sw_phy2>;
};
lan4: port@3 {
phy-handle = <&sw_phy3>;
};
lan5: port@4 {
phy-handle = <&sw_phy4>;
};
};
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
reg = <0>;
compatible = "microchip,ksz-mdio";
#address-cells = <1>;
#size-cells = <0>;
sw_phy0: ethernet-phy@0 {
reg = <0x0>;
};
sw_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sw_phy2: ethernet-phy@2 {
reg = <0x2>;
};
sw_phy3: ethernet-phy@3 {
reg = <0x3>;
};
sw_phy4: ethernet-phy@4 {
reg = <0x4>;
};
};
};
};
&usdhc2 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
assigned-clock-rates = <400000000>;
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
sd-uhs-ddr50;
sd-uhs-sdr104;
u-boot,dm-spl;
};
&usdhc3 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
assigned-clock-rates = <400000000>;
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};