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012522fef3
Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, MDHA, SKHA, INTC, and FlexBus structures and definitions in immap_5xxx.h to more unify modules header files. Append DSPI support for m547x_8x. SSI cleanup. Remove USB Host structure from immap_539.h. Apply changes to use FlexBus structures in mcf52x2's cpu_init.c and platform configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
254 lines
7.5 KiB
C
254 lines
7.5 KiB
C
/*
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* MCF5227x Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5227X__
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#define __IMMAP_5227X__
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/* Module Base Addresses */
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#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
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#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
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#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
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#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000)
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#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000)
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#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010)
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#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070)
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#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
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#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
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#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
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#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000)
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#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
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#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
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#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
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#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
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#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
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#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
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#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
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#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
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#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
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#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
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#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
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#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000)
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#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000)
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#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
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#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
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#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
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#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000)
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#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000)
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#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800)
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#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00)
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#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000)
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#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100)
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#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140)
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#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0)
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#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
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#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
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#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
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#include <asm/coldfire/crossbar.h>
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#include <asm/coldfire/dspi.h>
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#include <asm/coldfire/edma.h>
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#include <asm/coldfire/eport.h>
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#include <asm/coldfire/flexbus.h>
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#include <asm/coldfire/flexcan.h>
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#include <asm/coldfire/intctrl.h>
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#include <asm/coldfire/lcd.h>
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#include <asm/coldfire/pwm.h>
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#include <asm/coldfire/ssi.h>
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/* Reset Controller Module (RCM) */
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typedef struct rcm {
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u8 rcr;
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u8 rsr;
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} rcm_t;
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/* Chip Configuration Module (CCM) */
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typedef struct ccm {
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u16 ccr; /* Chip Configuration (Rd-only) */
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u16 resv1;
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u16 rcon; /* Reset Configuration (Rd-only) */
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u16 cir; /* Chip Identification (Rd-only) */
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u32 resv2;
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u16 misccr; /* Miscellaneous Control */
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u16 cdr; /* Clock Divider */
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u16 uocsr; /* USB On-the-Go Controller Status */
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u16 resv4;
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u16 sbfsr; /* Serial Boot Status */
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u16 sbfcr; /* Serial Boot Control */
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} ccm_t;
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typedef struct canex_ctrl {
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can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
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u32 res0[0x700]; /* 0x100 */
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can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */
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} canex_t;
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/* General Purpose I/O Module (GPIO) */
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typedef struct gpio {
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/* Port Output Data Registers */
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u8 podr_be; /* 0x00 */
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u8 podr_cs; /* 0x01 */
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u8 podr_fbctl; /* 0x02 */
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u8 podr_i2c; /* 0x03 */
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u8 rsvd1; /* 0x04 */
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u8 podr_uart; /* 0x05 */
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u8 podr_dspi; /* 0x06 */
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u8 podr_timer; /* 0x07 */
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u8 podr_lcdctl; /* 0x08 */
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u8 podr_lcddatah; /* 0x09 */
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u8 podr_lcddatam; /* 0x0A */
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u8 podr_lcddatal; /* 0x0B */
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/* Port Data Direction Registers */
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u8 pddr_be; /* 0x0C */
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u8 pddr_cs; /* 0x0D */
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u8 pddr_fbctl; /* 0x0E */
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u8 pddr_i2c; /* 0x0F */
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u8 rsvd2; /* 0x10 */
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u8 pddr_uart; /* 0x11 */
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u8 pddr_dspi; /* 0x12 */
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u8 pddr_timer; /* 0x13 */
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u8 pddr_lcdctl; /* 0x14 */
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u8 pddr_lcddatah; /* 0x15 */
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u8 pddr_lcddatam; /* 0x16 */
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u8 pddr_lcddatal; /* 0x17 */
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/* Port Pin Data/Set Data Registers */
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u8 ppdsdr_be; /* 0x18 */
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u8 ppdsdr_cs; /* 0x19 */
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u8 ppdsdr_fbctl; /* 0x1A */
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u8 ppdsdr_i2c; /* 0x1B */
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u8 rsvd3; /* 0x1C */
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u8 ppdsdr_uart; /* 0x1D */
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u8 ppdsdr_dspi; /* 0x1E */
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u8 ppdsdr_timer; /* 0x1F */
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u8 ppdsdr_lcdctl; /* 0x20 */
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u8 ppdsdr_lcddatah; /* 0x21 */
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u8 ppdsdr_lcddatam; /* 0x22 */
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u8 ppdsdr_lcddatal; /* 0x23 */
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/* Port Clear Output Data Registers */
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u8 pclrr_be; /* 0x24 */
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u8 pclrr_cs; /* 0x25 */
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u8 pclrr_fbctl; /* 0x26 */
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u8 pclrr_i2c; /* 0x27 */
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u8 rsvd4; /* 0x28 */
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u8 pclrr_uart; /* 0x29 */
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u8 pclrr_dspi; /* 0x2A */
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u8 pclrr_timer; /* 0x2B */
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u8 pclrr_lcdctl; /* 0x2C */
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u8 pclrr_lcddatah; /* 0x2D */
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u8 pclrr_lcddatam; /* 0x2E */
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u8 pclrr_lcddatal; /* 0x2F */
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/* Pin Assignment Registers */
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u8 par_be; /* 0x30 */
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u8 par_cs; /* 0x31 */
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u8 par_fbctl; /* 0x32 */
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u8 par_i2c; /* 0x33 */
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u16 par_uart; /* 0x34 */
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u8 par_dspi; /* 0x36 */
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u8 par_timer; /* 0x37 */
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u8 par_lcdctl; /* 0x38 */
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u8 par_irq; /* 0x39 */
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u16 rsvd6; /* 0x3A - 0x3B */
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u32 par_lcdh; /* 0x3C */
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u32 par_lcdl; /* 0x40 */
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/* Mode select control registers */
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u8 mscr_fb; /* 0x44 */
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u8 mscr_sdram; /* 0x45 */
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u16 rsvd7; /* 0x46 - 0x47 */
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u8 dscr_dspi; /* 0x48 */
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u8 dscr_timer; /* 0x49 */
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u8 dscr_i2c; /* 0x4A */
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u8 dscr_lcd; /* 0x4B */
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u8 dscr_debug; /* 0x4C */
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u8 dscr_clkrst; /* 0x4D */
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u8 dscr_irq; /* 0x4E */
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u8 dscr_uart; /* 0x4F */
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} gpio_t;
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/* SDRAM Controller (SDRAMC) */
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typedef struct sdramc {
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u32 sdmr; /* Mode/Extended Mode */
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u32 sdcr; /* Control */
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u32 sdcfg1; /* Configuration 1 */
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u32 sdcfg2; /* Chip Select */
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u8 resv0[0x100];
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u32 sdcs0; /* Mode/Extended Mode */
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u32 sdcs1; /* Mode/Extended Mode */
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} sdramc_t;
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/* Phase Locked Loop (PLL) */
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typedef struct pll {
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u32 pcr; /* PLL Control */
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u32 psr; /* PLL Status */
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} pll_t;
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/* System Control Module register */
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typedef struct scm1 {
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u32 mpr; /* 0x00 Master Privilege */
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u32 rsvd1[7];
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u32 pacra; /* 0x20 */
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u32 pacrb; /* 0x24 */
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u32 pacrc; /* 0x28 */
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u32 pacrd; /* 0x2C */
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u32 rsvd2[4];
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u32 pacre; /* 0x40 */
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u32 pacrf; /* 0x44 */
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u32 pacrg; /* 0x48 */
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u32 rsvd3;
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u32 pacri; /* 0x50 */
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} scm1_t;
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typedef struct scm2_ctrl {
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u8 res1[3]; /* 0x00 - 0x02 */
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u8 wcr; /* 0x03 wakeup control */
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u16 res2; /* 0x04 - 0x05 */
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u16 cwcr; /* 0x06 Core Watchdog Control */
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u8 res3[3]; /* 0x08 - 0x0A */
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u8 cwsr; /* 0x0B Core Watchdog Service */
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u8 res4[2]; /* 0x0C - 0x0D */
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u8 scmisr; /* 0x0F Interrupt Status */
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u32 res5; /* 0x20 */
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u32 bcr; /* 0x24 Burst Configuration */
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} scm2_t;
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typedef struct scm3_ctrl {
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u32 cfadr; /* 0x00 Core Fault Address */
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u8 res7; /* 0x04 */
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u8 cfier; /* 0x05 Core Fault Interrupt Enable */
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u8 cfloc; /* 0x06 Core Fault Location */
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u8 cfatr; /* 0x07 Core Fault Attributes */
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u32 cfdtr; /* 0x08 Core Fault Data */
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} scm3_t;
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typedef struct rtcex {
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u32 rsvd1[3];
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u32 gocu;
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u32 gocl;
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} rtcex_t;
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#endif /* __IMMAP_5227X__ */
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