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3a85e03f83
Provide the required settings for the debug UART. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com>
365 lines
12 KiB
ReStructuredText
365 lines
12 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+
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.. Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
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MAIX
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====
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Several of the Sipeed Maix series of boards cotain the Kendryte K210 processor,
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a 64-bit RISC-V CPU. This processor contains several peripherals to accelerate
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neural network processing and other "ai" tasks. This includes a "KPU" neural
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network processor, an audio processor supporting beamforming reception, and a
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digital video port supporting capture and output at VGA resolution. Other
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peripherals include 8M of SRAM (accessible with and without caching); remappable
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pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller;
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and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash;
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on-board usb-serial bridges; ports for cameras, displays, and sd cards; and
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ESP32 chips.
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Currently, only the Sipeed MAIX BiT V2.0 (bitm) and Sipeed MAIXDUINO are
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supported, but the boards are fairly similar.
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Documentation for Maix boards is available from
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`Sipeed's website <http://dl.sipeed.com/MAIX/HDK/>`_.
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Documentation for the Kendryte K210 is available from
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`Kendryte's website <https://kendryte.com/downloads/>`_. However, hardware
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details are rather lacking, so most technical reference has been taken from the
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`standalone sdk <https://github.com/kendryte/kendryte-standalone-sdk>`_.
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Build and boot steps
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--------------------
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To build U-Boot, run
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.. code-block:: none
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make <defconfig>
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make CROSS_COMPILE=<your cross compile prefix>
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To flash U-Boot, run
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.. code-block:: none
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kflash -tp /dev/<your tty here> -B <board_id> u-boot-dtb.bin
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The board provides two serial devices, e.g.
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* /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if00-port0
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* /dev/serial/by-id/usb-Kongou_Hikari_Sipeed-Debug_12345678AB-if01-port0
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Which one is used for flashing depends on the board.
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Currently only a small subset of the board features are supported. So we can
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use the same default configuration and device tree. In the long run we may need
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separate settings.
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======================== ========================== ========== ==========
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Board defconfig board_id TTY device
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======================== ========================== ========== ==========
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Sipeed MAIX BiT sipeed_maix_bitm_defconfig bit first
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Sipeed MAIX BiT with Mic sipeed_maix_bitm_defconfig bit_mic first
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Sipeed MAIXDUINO sipeed_maix_bitm_defconfig maixduino first
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Sipeed MAIX GO goE second
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Sipeed MAIX ONE DOCK goD first
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======================== ========================== ========== ==========
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Flashing causes a reboot of the device. Parameter -t specifies that the serial
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console shall be opened immediately. Boot output should look like the following:
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.. code-block:: none
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U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
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DRAM: 8 MiB
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In: serial@38000000
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Out: serial@38000000
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Err: serial@38000000
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=>
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Loading Images
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^^^^^^^^^^^^^^
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To load a kernel, transfer it over serial.
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.. code-block:: none
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=> loady 80000000 1500000
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## Switch baudrate to 1500000 bps and press ENTER ...
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*** baud: 1500000
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*** baud: 1500000 ***
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## Ready for binary (ymodem) download to 0x80000000 at 1500000 bps...
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C
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*** file: loader.bin
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$ sz -vv loader.bin
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Sending: loader.bin
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Bytes Sent:2478208 BPS:72937
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Sending:
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Ymodem sectors/kbytes sent: 0/ 0k
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Transfer complete
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*** exit status: 0 ***
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## Total Size = 0x0025d052 = 2478162 Bytes
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## Switch baudrate to 115200 bps and press ESC ...
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*** baud: 115200
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*** baud: 115200 ***
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=>
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Running Programs
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^^^^^^^^^^^^^^^^
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Binaries
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""""""""
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To run a bare binary, use the ``go`` command:
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.. code-block:: none
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=> loady
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## Ready for binary (ymodem) download to 0x80000000 at 115200 bps...
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C
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*** file: ./examples/standalone/hello_world.bin
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$ sz -vv ./examples/standalone/hello_world.bin
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Sending: hello_world.bin
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Bytes Sent: 4864 BPS:649
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Sending:
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Ymodem sectors/kbytes sent: 0/ 0k
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Transfer complete
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*** exit status: 0 ***
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(CAN) packets, 5 retries
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## Total Size = 0x000012f8 = 4856 Bytes
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=> go 80000000
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## Starting application at 0x80000000 ...
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Example expects ABI version 9
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Actual U-Boot ABI version 9
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Hello World
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argc = 1
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argv[0] = "80000000"
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argv[1] = "<NULL>"
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Hit any key to exit ...
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Legacy Images
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"""""""""""""
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To run legacy images, use the ``bootm`` command:
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.. code-block:: none
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$ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 80000000 -e 80000000 -d examples/standalone/hello_world.bin hello_world.img
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Image Name:
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Created: Thu Mar 5 12:04:10 2020
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Image Type: RISC-V U-Boot Standalone Program (uncompressed)
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Data Size: 4856 Bytes = 4.74 KiB = 0.00 MiB
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Load Address: 80000000
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Entry Point: 80000000
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$ picocom -b 115200 /dev/ttyUSB0i
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=> loady
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## Ready for binary (ymodem) download to 0x80000000 at 115200 bps...
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C
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*** file: hello_world.img
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$ sz -vv hello_world.img
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Sending: hello_world.img
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Bytes Sent: 4992 BPS:665
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Sending:
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Ymodem sectors/kbytes sent: 0/ 0k
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Transfer complete
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*** exit status: 0 ***
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CAN) packets, 3 retries
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## Total Size = 0x00001338 = 4920 Bytes
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=> bootm
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## Booting kernel from Legacy Image at 80000000 ...
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Image Name:
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Image Type: RISC-V U-Boot Standalone Program (uncompressed)
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Data Size: 4856 Bytes = 4.7 KiB
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Load Address: 80000000
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Entry Point: 80000000
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Verifying Checksum ... OK
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Loading Standalone Program
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Example expects ABI version 9
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Actual U-Boot ABI version 9
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Hello World
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argc = 0
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argv[0] = "<NULL>"
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Hit any key to exit ...
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Over- and Under-clocking
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------------------------
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To change the clock speed of the K210, you will need to enable
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``CONFIG_CLK_K210_SET_RATE`` and edit the board's device tree. To do this, add a
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section to ``arch/riscv/arch/riscv/dts/k210-maix-bit.dts`` like the following:
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.. code-block:: none
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&sysclk {
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assigned-clocks = <&sysclk K210_CLK_PLL0>;
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assigned-clock-rates = <800000000>;
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};
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There are three PLLs on the K210: PLL0 is the parent of most of the components,
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including the CPU and RAM. PLL1 is the parent of the neural network coprocessor.
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PLL2 is the parent of the sound processing devices. Note that child clocks of
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PLL0 and PLL2 run at *half* the speed of the PLLs. For example, if PLL0 is
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running at 800 MHz, then the CPU will run at 400 MHz. This is the example given
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above. The CPU can be overclocked to around 600 MHz, and underclocked to 26 MHz.
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It is possible to set PLL2's parent to PLL0. The plls are more accurate when
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converting between similar frequencies. This makes it easier to get an accurate
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frequency for I2S. As an example, consider sampling an I2S device at 44.1 kHz.
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On this device, the I2S serial clock runs at 64 times the sample rate.
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Therefore, we would like to run PLL2 at an even multiple of 2.8224 MHz. If
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PLL2's parent is IN0, we could use a frequency of 390 MHz (the same as the CPU's
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default speed). Dividing by 138 yields a serial clock of about 2.8261 MHz. This
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results in a sample rate of 44.158 kHz---around 50 Hz or .1% too fast. If,
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instead, we set PLL2's parent to PLL1 running at 390 MHz, and request a rate of
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2.8224 * 136 = 383.8464 MHz, the achieved rate is 383.90625 MHz. Dividing by 136
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yields a serial clock of about 2.8228 MHz. This results in a sample rate of
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44.107 kHz---just 7 Hz or .02% too fast. This configuration is shown in the
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following example:
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.. code-block:: none
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&sysclk {
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assigned-clocks = <&sysclk K210_CLK_PLL1>, <&sysclk K210_CLK_PLL2>;
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assigned-clock-parents = <0>, <&sysclk K210_CLK_PLL1>;
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assigned-clock-rates = <390000000>, <383846400>;
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};
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There are a couple of quirks to the PLLs. First, there are more frequency ratios
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just above and below 1.0, but there is a small gap around 1.0. To be explicit,
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if the input frequency is 100 MHz, it would be impossible to have an output of
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99 or 101 MHz. In addition, there is a maximum frequency for the internal VCO,
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so higher input/output frequencies will be less accurate than lower ones.
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Technical Details
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-----------------
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Boot Sequence
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^^^^^^^^^^^^^
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1. ``RESET`` pin is deasserted.
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2. Both harts begin executing at ``0x00001000``.
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3. Both harts jump to firmware at ``0x88000000``.
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4. One hart is chosen as a boot hart.
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5. Firmware reads value of pin ``IO_16`` (ISP).
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* If the pin is low, enter ISP mode. This mode allows loading data to ram,
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writing it to flash, and booting from specific addresses.
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* If the pin is high, continue boot.
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6. Firmware reads the next stage from flash (SPI3) to address ``0x80000000``.
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* If byte 0 is 1, the next stage is decrypted using the built-in AES
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accelerator and the one-time programmable, 128-bit AES key.
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* Bytes 1 to 4 hold the length of the next stage.
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* The SHA-256 sum of the next stage is automatically calculated, and verified
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against the 32 bytes following the next stage.
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7. The boot hart sends an IPI to the other hart telling it to jump to the next
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stage.
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8. The boot hart jumps to ``0x80000000``.
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Debug UART
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^^^^^^^^^^
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The Debug UART is provided with the following settings::
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_SIFIVE=y
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CONFIG_DEBUG_UART_BASE=0x38000000
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CONFIG_DEBUG_UART_CLOCK=390000000
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Resetting the board
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^^^^^^^^^^^^^^^^^^^
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The MAIX boards can be reset using the DTR and RTS lines of the serial console.
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How the lines are used depends on the specific board. See the code of kflash.py
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for details.
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This is the reset sequence for the MAXDUINO and MAIX BiT with Mic:
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.. code-block:: python
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def reset(self):
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self.device.setDTR(False)
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self.device.setRTS(False)
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time.sleep(0.1)
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self.device.setDTR(True)
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time.sleep(0.1)
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self.device.setDTR(False)
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time.sleep(0.1)
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and this for the MAIX Bit:
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.. code-block:: python
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def reset(self):
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self.device.setDTR(False)
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self.device.setRTS(False)
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time.sleep(0.1)
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self.device.setRTS(True)
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time.sleep(0.1)
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self.device.setRTS(False)
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time.sleep(0.1)
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Memory Map
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^^^^^^^^^^
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========== ========= ===========
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Address Size Description
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========== ========= ===========
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0x00000000 0x1000 debug
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0x00001000 0x1000 rom
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0x02000000 0xC000 clint
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0x0C000000 0x4000000 plic
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0x38000000 0x1000 uarths
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0x38001000 0x1000 gpiohs
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0x40000000 0x400000 sram0 (non-cached)
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0x40400000 0x200000 sram1 (non-cached)
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0x40600000 0x200000 airam (non-cached)
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0x40800000 0xC00000 kpu
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0x42000000 0x400000 fft
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0x50000000 0x1000 dmac
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0x50200000 0x200000 apb0
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0x50200000 0x80 gpio
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0x50210000 0x100 uart0
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0x50220000 0x100 uart1
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0x50230000 0x100 uart2
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0x50240000 0x100 spi slave
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0x50250000 0x200 i2s0
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0x50250200 0x200 apu
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0x50260000 0x200 i2s1
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0x50270000 0x200 i2s2
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0x50280000 0x100 i2c0
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0x50290000 0x100 i2c1
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0x502A0000 0x100 i2c2
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0x502B0000 0x100 fpioa
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0x502C0000 0x100 sha256
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0x502D0000 0x100 timer0
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0x502E0000 0x100 timer1
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0x502F0000 0x100 timer2
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0x50400000 0x200000 apb1
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0x50400000 0x100 wdt0
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0x50410000 0x100 wdt1
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0x50420000 0x100 otp control
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0x50430000 0x100 dvp
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0x50440000 0x100 sysctl
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0x50450000 0x100 aes
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0x50460000 0x100 rtc
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0x52000000 0x4000000 apb2
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0x52000000 0x100 spi0
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0x53000000 0x100 spi1
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0x54000000 0x200 spi3
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0x80000000 0x400000 sram0 (cached)
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0x80400000 0x200000 sram1 (cached)
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0x80600000 0x200000 airam (cached)
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0x88000000 0x20000 otp
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0x88000000 0xC200 firmware
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0x8801C000 0x1000 riscv priv spec 1.9 config
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0x8801D000 0x2000 flattened device tree (contains only addresses and
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interrupts)
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0x8801f000 0x1000 credits
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========== ========= ===========
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