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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
133 lines
3.9 KiB
C
133 lines
3.9 KiB
C
/*
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* Copyright (C) 2001 - 2007 Tensilica Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_PTRACE_H
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#define _XTENSA_PTRACE_H
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#include <compiler.h>
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/*
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* Kernel stack
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*
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* +-----------------------+ -------- STACK_SIZE
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* | register file | |
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* +-----------------------+ |
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* | struct pt_regs | |
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* +-----------------------+ | ------ PT_REGS_OFFSET
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* double : 16 bytes spill area : | ^
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* exception :- - - - - - - - - - - -: | |
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* frame : struct pt_regs : | |
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* :- - - - - - - - - - - -: | |
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* | | | |
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* | memory stack | | |
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* | | | |
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* ~ ~ ~ ~
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* ~ ~ ~ ~
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* | | | |
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* | | | |
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* +-----------------------+ | | --- STACK_BIAS
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* | struct task_struct | | | ^
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* current --> +-----------------------+ | | |
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* | struct thread_info | | | |
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* +-----------------------+ --------
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*/
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#define KERNEL_STACK_SIZE (2 * PAGE_SIZE)
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/* Offsets for exception_handlers[] (3 x 64-entries x 4-byte tables) */
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#define EXC_TABLE_KSTK 0x004 /* Kernel Stack */
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#define EXC_TABLE_DOUBLE_SAVE 0x008 /* Double exception save area for a0 */
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#define EXC_TABLE_FIXUP 0x00c /* Fixup handler */
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#define EXC_TABLE_PARAM 0x010 /* For passing a parameter to fixup */
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#define EXC_TABLE_SYSCALL_SAVE 0x014 /* For fast syscall handler */
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#define EXC_TABLE_FAST_USER 0x100 /* Fast user exception handler */
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#define EXC_TABLE_FAST_KERNEL 0x200 /* Fast kernel exception handler */
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#define EXC_TABLE_DEFAULT 0x300 /* Default C-Handler */
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#define EXC_TABLE_SIZE 0x400
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/* Registers used by strace */
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#define REG_A_BASE 0xfc000000
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#define REG_AR_BASE 0x04000000
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#define REG_PC 0x14000000
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#define REG_PS 0x080000e6
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#define REG_WB 0x08000048
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#define REG_WS 0x08000049
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#define REG_LBEG 0x08000000
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#define REG_LEND 0x08000001
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#define REG_LCOUNT 0x08000002
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#define REG_SAR 0x08000003
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#define REG_DEPC 0x080000c0
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#define REG_EXCCAUSE 0x080000e8
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#define REG_EXCVADDR 0x080000ee
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#define SYSCALL_NR 0x1
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#define AR_REGNO_TO_A_REGNO(ar, wb) (ar - wb*4) & ~(XCHAL_NUM_AREGS - 1)
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/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */
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#define PTRACE_GETREGS 12
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#define PTRACE_SETREGS 13
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#define PTRACE_GETFPREGS 14
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#define PTRACE_SETFPREGS 15
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#define PTRACE_GETFPREGSIZE 18
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#ifndef __ASSEMBLY__
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/*
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* This struct defines the way the registers are stored on the
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* kernel stack during a system call or other kernel entry.
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*/
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struct pt_regs {
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unsigned long pc; /* 4 */
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unsigned long ps; /* 8 */
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unsigned long depc; /* 12 */
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unsigned long exccause; /* 16 */
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unsigned long excvaddr; /* 20 */
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unsigned long debugcause; /* 24 */
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unsigned long wmask; /* 28 */
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unsigned long lbeg; /* 32 */
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unsigned long lend; /* 36 */
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unsigned long lcount; /* 40 */
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unsigned long sar; /* 44 */
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unsigned long windowbase; /* 48 */
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unsigned long windowstart; /* 52 */
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unsigned long syscall; /* 56 */
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unsigned long icountlevel; /* 60 */
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int reserved[1]; /* 64 */
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/* Make sure the areg field is 16 bytes aligned */
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int align[0] __aligned(16);
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/* current register frame.
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* Note: The ESF for kernel exceptions ends after 16 registers!
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*/
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unsigned long areg[16]; /* 128 (64) */
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};
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#ifdef __KERNEL__
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# define task_pt_regs(tsk) ((struct pt_regs *) \
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(task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1)
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# define user_mode(regs) (((regs)->ps & 0x00000020) != 0)
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# define instruction_pointer(regs) ((regs)->pc)
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void show_regs(struct pt_regs *);
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# ifndef CONFIG_SMP
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# define profile_pc(regs) instruction_pointer(regs)
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# endif
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#endif /* __KERNEL__ */
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#else /* __ASSEMBLY__ */
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#ifdef __KERNEL__
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# include <asm/asm-offsets.h>
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#define PT_REGS_OFFSET (KERNEL_STACK_SIZE - PT_USER_SIZE)
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#endif
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#endif /* !__ASSEMBLY__ */
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#endif /* _XTENSA_PTRACE_H */
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