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280057bd7d
With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
126 lines
2.3 KiB
C
126 lines
2.3 KiB
C
/*
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* (C) Copyright 2016
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* Vikas Manocha, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _STM32_GPIO_H_
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#define _STM32_GPIO_H_
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#include <asm/gpio.h>
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enum stm32_gpio_port {
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STM32_GPIO_PORT_A = 0,
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STM32_GPIO_PORT_B,
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STM32_GPIO_PORT_C,
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STM32_GPIO_PORT_D,
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STM32_GPIO_PORT_E,
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STM32_GPIO_PORT_F,
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STM32_GPIO_PORT_G,
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STM32_GPIO_PORT_H,
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STM32_GPIO_PORT_I
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};
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enum stm32_gpio_pin {
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STM32_GPIO_PIN_0 = 0,
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STM32_GPIO_PIN_1,
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STM32_GPIO_PIN_2,
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STM32_GPIO_PIN_3,
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STM32_GPIO_PIN_4,
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STM32_GPIO_PIN_5,
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STM32_GPIO_PIN_6,
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STM32_GPIO_PIN_7,
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STM32_GPIO_PIN_8,
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STM32_GPIO_PIN_9,
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STM32_GPIO_PIN_10,
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STM32_GPIO_PIN_11,
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STM32_GPIO_PIN_12,
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STM32_GPIO_PIN_13,
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STM32_GPIO_PIN_14,
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STM32_GPIO_PIN_15
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};
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enum stm32_gpio_mode {
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STM32_GPIO_MODE_IN = 0,
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STM32_GPIO_MODE_OUT,
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STM32_GPIO_MODE_AF,
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STM32_GPIO_MODE_AN
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};
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enum stm32_gpio_otype {
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STM32_GPIO_OTYPE_PP = 0,
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STM32_GPIO_OTYPE_OD
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};
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enum stm32_gpio_speed {
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STM32_GPIO_SPEED_2M = 0,
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STM32_GPIO_SPEED_25M,
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STM32_GPIO_SPEED_50M,
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STM32_GPIO_SPEED_100M
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};
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enum stm32_gpio_pupd {
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STM32_GPIO_PUPD_NO = 0,
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STM32_GPIO_PUPD_UP,
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STM32_GPIO_PUPD_DOWN
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};
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enum stm32_gpio_af {
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STM32_GPIO_AF0 = 0,
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STM32_GPIO_AF1,
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STM32_GPIO_AF2,
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STM32_GPIO_AF3,
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STM32_GPIO_AF4,
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STM32_GPIO_AF5,
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STM32_GPIO_AF6,
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STM32_GPIO_AF7,
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STM32_GPIO_AF8,
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STM32_GPIO_AF9,
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STM32_GPIO_AF10,
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STM32_GPIO_AF11,
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STM32_GPIO_AF12,
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STM32_GPIO_AF13,
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STM32_GPIO_AF14,
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STM32_GPIO_AF15
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};
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struct stm32_gpio_dsc {
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enum stm32_gpio_port port;
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enum stm32_gpio_pin pin;
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};
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struct stm32_gpio_ctl {
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enum stm32_gpio_mode mode;
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enum stm32_gpio_otype otype;
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enum stm32_gpio_speed speed;
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enum stm32_gpio_pupd pupd;
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enum stm32_gpio_af af;
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};
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struct stm32_gpio_regs {
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u32 moder; /* GPIO port mode */
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u32 otyper; /* GPIO port output type */
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u32 ospeedr; /* GPIO port output speed */
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u32 pupdr; /* GPIO port pull-up/pull-down */
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u32 idr; /* GPIO port input data */
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u32 odr; /* GPIO port output data */
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u32 bsrr; /* GPIO port bit set/reset */
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u32 lckr; /* GPIO port configuration lock */
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u32 afr[2]; /* GPIO alternate function */
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};
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struct stm32_gpio_priv {
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struct stm32_gpio_regs *regs;
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};
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static inline unsigned stm32_gpio_to_port(unsigned gpio)
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{
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return gpio / 16;
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}
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static inline unsigned stm32_gpio_to_pin(unsigned gpio)
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{
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return gpio % 16;
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}
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#endif /* _STM32_GPIO_H_ */
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