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fdff1f96a6
The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
12 lines
241 B
Text
12 lines
241 B
Text
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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config GENERIC_RISCV
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bool
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select ARCH_EARLY_INIT_R
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER
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imply SIFIVE_CLINT if RISCV_MMODE
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imply CMD_CPU
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