mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 13:14:27 +00:00
d96a782d09
The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol. When no other boot medium are available (or by forcing the USB mode), the ROM sets the primary USB port as device mode and waits for a Host to enumerate. When enumerated, a custom protocol described at [1] permits writing to memory and execute some specific FIP init code to run the loaded Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage. In this mode, we can load different binaries that can be used by U-boot like a script image file. This adds support for a custom USB boot stage only available when the boot mode is USB and the script file at a pre-defined address is valid. This support was heavily copied from the Sunxi Allwinner FEL U-Boot support. The tool pyamlboot described at [2], permits using this boot mode on boards exposing the first USB port, either as OTG or Host port. [1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md [2] https://github.com/superna9999/pyamlboot/blob/master/README.md Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
118 lines
3 KiB
C
118 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
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* (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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#include <asm/arch/boot.h>
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#include <asm/arch/eth.h>
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#include <asm/arch/axg.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/armv8/mmu.h>
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#include <linux/sizes.h>
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#include <phy.h>
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DECLARE_GLOBAL_DATA_PTR;
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int meson_get_boot_device(void)
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{
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return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
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}
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/* Configure the reserved memory zones exported by the secure registers
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* into EFI and DTB reserved memory entries.
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*/
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void meson_init_reserved_memory(void *fdt)
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{
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u64 bl31_size, bl31_start;
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u64 bl32_size, bl32_start;
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u32 reg;
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/*
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* Get ARM Trusted Firmware reserved memory zones in :
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* - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
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* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
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* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
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*/
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reg = readl(AXG_AO_SEC_GP_CFG3);
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bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
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>> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
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bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
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bl31_start = readl(AXG_AO_SEC_GP_CFG5);
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bl32_start = readl(AXG_AO_SEC_GP_CFG4);
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/* Add BL31 reserved zone */
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if (bl31_start && bl31_size)
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meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
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/* Add BL32 reserved zone */
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if (bl32_start && bl32_size)
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meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
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}
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phys_size_t get_effective_memsize(void)
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{
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/* Size is reported in MiB, convert it in bytes */
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return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
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>> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
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}
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static struct mm_region axg_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf0000000UL,
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.phys = 0xf0000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = axg_mem_map;
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/* Configure the Ethernet MAC with the requested interface mode
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* with some optional flags.
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*/
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void meson_eth_init(phy_interface_t mode, unsigned int flags)
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{
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switch (mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* Set RGMII mode */
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setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
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AXG_ETH_REG_0_TX_PHASE(1) |
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AXG_ETH_REG_0_TX_RATIO(4) |
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AXG_ETH_REG_0_PHY_CLK_EN |
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AXG_ETH_REG_0_CLK_EN);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* Set RMII mode */
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out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
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AXG_ETH_REG_0_INVERT_RMII_CLK |
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AXG_ETH_REG_0_CLK_EN);
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break;
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default:
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printf("Invalid Ethernet interface mode\n");
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return;
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}
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/* Enable power gate */
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clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
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}
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