mirror of
https://github.com/AsahiLinux/u-boot
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13ba6d0e6f
Synchronize stm32h7 device tree with kernel v4.20. U-boot DT files and pinctrl bindings are updated, useless nodes are removed and gpio compatible added. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
223 lines
6.1 KiB
Text
223 lines
6.1 KiB
Text
/*
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* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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/ {
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soc {
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32h743-pinctrl";
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ranges = <0 0x58020000 0x3000>;
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interrupt-parent = <&exti>;
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st,syscfg = <&syscfg 0x8>;
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pins-are-numbered;
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gpioa: gpio@58020000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc GPIOA_CK>;
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st,bank-name = "GPIOA";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpiob: gpio@58020400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x400 0x400>;
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clocks = <&rcc GPIOB_CK>;
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st,bank-name = "GPIOB";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpioc: gpio@58020800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x800 0x400>;
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clocks = <&rcc GPIOC_CK>;
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st,bank-name = "GPIOC";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpiod: gpio@58020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0xc00 0x400>;
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clocks = <&rcc GPIOD_CK>;
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st,bank-name = "GPIOD";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpioe: gpio@58021000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc GPIOE_CK>;
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st,bank-name = "GPIOE";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpiof: gpio@58021400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1400 0x400>;
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clocks = <&rcc GPIOF_CK>;
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st,bank-name = "GPIOF";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpiog: gpio@58021800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1800 0x400>;
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clocks = <&rcc GPIOG_CK>;
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st,bank-name = "GPIOG";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpioh: gpio@58021c00 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1c00 0x400>;
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clocks = <&rcc GPIOH_CK>;
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st,bank-name = "GPIOH";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpioi: gpio@58022000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&rcc GPIOI_CK>;
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st,bank-name = "GPIOI";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpioj: gpio@58022400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x2400 0x400>;
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clocks = <&rcc GPIOJ_CK>;
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st,bank-name = "GPIOJ";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpiok: gpio@58022800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x2800 0x400>;
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clocks = <&rcc GPIOK_CK>;
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st,bank-name = "GPIOK";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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i2c1_pins_a: i2c1@0 {
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pins {
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pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
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<STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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usart1_pins: usart1@0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
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bias-disable;
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};
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};
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usart2_pins: usart2@0 {
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pins1 {
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pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
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bias-disable;
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};
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};
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usbotg_hs_pins_a: usbotg-hs@0 {
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pins {
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pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
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<STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
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<STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
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<STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
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<STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
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<STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
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<STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
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<STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
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<STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
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<STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
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<STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
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<STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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};
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};
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};
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