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https://github.com/AsahiLinux/u-boot
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834e91af43
Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
158 lines
3.6 KiB
C
158 lines
3.6 KiB
C
/*
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* OMAP USB HOST xHCI Controller
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* Author: Dan Murphy <dmurphy@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <usb.h>
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#include <asm-generic/errno.h>
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#include <asm/omap_common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/compat.h>
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#include <linux/usb/dwc3.h>
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#include <linux/usb/xhci-omap.h>
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#include "xhci.h"
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/* Declare global data pointer */
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DECLARE_GLOBAL_DATA_PTR;
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static struct omap_xhci omap;
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inline int __board_usb_init(int index, enum board_usb_init_type init)
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{
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return 0;
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}
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int board_usb_init(int index, enum board_usb_init_type init) \
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__attribute__((weak, alias("__board_usb_init")));
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static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
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{
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clrsetbits_le32(&dwc3_reg->g_ctl,
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DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
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DWC3_GCTL_PRTCAPDIR(mode));
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}
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static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
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{
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/* Before Resetting PHY, put Core in Reset */
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setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
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omap_reset_usb_phy(dwc3_reg);
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/* After PHYs are stable we can take Core out of reset state */
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clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
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}
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static int dwc3_core_init(struct dwc3 *dwc3_reg)
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{
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u32 reg;
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u32 revision;
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unsigned int dwc3_hwparams1;
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revision = readl(&dwc3_reg->g_snpsid);
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/* This should read as U3 followed by revision number */
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if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
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puts("this is not a DesignWare USB3 DRD Core\n");
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return -1;
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}
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dwc3_core_soft_reset(dwc3_reg);
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dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
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reg = readl(&dwc3_reg->g_ctl);
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reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
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reg &= ~DWC3_GCTL_DISSCRAMBLE;
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switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
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case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
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reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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break;
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default:
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debug("No power optimization available\n");
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}
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/*
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* WORKAROUND: DWC3 revisions <1.90a have a bug
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* where the device can fail to connect at SuperSpeed
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* and falls back to high-speed mode which causes
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* the device to enter a Connect/Disconnect loop
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*/
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if ((revision & DWC3_REVISION_MASK) < 0x190a)
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reg |= DWC3_GCTL_U2RSTECN;
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writel(reg, &dwc3_reg->g_ctl);
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return 0;
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}
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static int omap_xhci_core_init(struct omap_xhci *omap)
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{
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int ret = 0;
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omap_enable_phy(omap);
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ret = dwc3_core_init(omap->dwc3_reg);
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if (ret) {
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debug("%s:failed to initialize core\n", __func__);
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return ret;
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}
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/* We are hard-coding DWC3 core to Host Mode */
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dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
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return ret;
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}
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static void omap_xhci_core_exit(struct omap_xhci *omap)
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{
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usb_phy_power(0);
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}
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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{
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struct omap_xhci *ctx = &omap;
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int ret = 0;
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ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE;
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
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ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE;
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ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE;
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ret = board_usb_init(index, USB_INIT_HOST);
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if (ret != 0) {
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puts("Failed to initialize board for USB\n");
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return ret;
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}
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ret = omap_xhci_core_init(ctx);
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if (ret < 0) {
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puts("Failed to initialize xhci\n");
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return ret;
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}
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*hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE);
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*hcor = (struct xhci_hcor *)((uint32_t) *hccr
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+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)*hccr, (uint32_t)*hcor,
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(uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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return ret;
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}
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void xhci_hcd_stop(int index)
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{
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struct omap_xhci *ctx = &omap;
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omap_xhci_core_exit(ctx);
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}
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