mirror of
https://github.com/AsahiLinux/u-boot
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3765b3e7bd
Signed-off-by: Wolfgang Denk <wd@denx.de>
171 lines
3.5 KiB
C
171 lines
3.5 KiB
C
/*
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* Copyright (C) 2011 Samsung Electronics
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*
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* Donghwa Lee <dh09.lee@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <pwm.h>
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#include <asm/io.h>
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#include <asm/arch/pwm.h>
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#include <asm/arch/clk.h>
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int pwm_enable(int pwm_id)
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{
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const struct s5p_timer *pwm =
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(struct s5p_timer *)samsung_get_base_timer();
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unsigned long tcon;
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tcon = readl(&pwm->tcon);
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tcon |= TCON_START(pwm_id);
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writel(tcon, &pwm->tcon);
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return 0;
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}
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void pwm_disable(int pwm_id)
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{
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const struct s5p_timer *pwm =
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(struct s5p_timer *)samsung_get_base_timer();
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unsigned long tcon;
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tcon = readl(&pwm->tcon);
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tcon &= ~TCON_START(pwm_id);
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writel(tcon, &pwm->tcon);
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}
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static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
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{
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unsigned long tin_parent_rate;
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unsigned int div;
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tin_parent_rate = get_pwm_clk();
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for (div = 2; div <= 16; div *= 2) {
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if ((tin_parent_rate / (div << 16)) < freq)
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return tin_parent_rate / div;
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}
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return tin_parent_rate / 16;
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}
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#define NS_IN_SEC 1000000000UL
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int pwm_config(int pwm_id, int duty_ns, int period_ns)
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{
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const struct s5p_timer *pwm =
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(struct s5p_timer *)samsung_get_base_timer();
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unsigned int offset;
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unsigned long tin_rate;
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unsigned long tin_ns;
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unsigned long frequency;
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unsigned long tcon;
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unsigned long tcnt;
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unsigned long tcmp;
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/*
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* We currently avoid using 64bit arithmetic by using the
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* fact that anything faster than 1GHz is easily representable
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* by 32bits.
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*/
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if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0)
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return -ERANGE;
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if (duty_ns > period_ns)
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return -EINVAL;
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frequency = NS_IN_SEC / period_ns;
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/* Check to see if we are changing the clock rate of the PWM */
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tin_rate = pwm_calc_tin(pwm_id, frequency);
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tin_ns = NS_IN_SEC / tin_rate;
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tcnt = period_ns / tin_ns;
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/* Note, counters count down */
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tcmp = duty_ns / tin_ns;
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tcmp = tcnt - tcmp;
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/* Update the PWM register block. */
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offset = pwm_id * 3;
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if (pwm_id < 4) {
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writel(tcnt, &pwm->tcntb0 + offset);
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writel(tcmp, &pwm->tcmpb0 + offset);
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}
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tcon = readl(&pwm->tcon);
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tcon |= TCON_UPDATE(pwm_id);
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if (pwm_id < 4)
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tcon |= TCON_AUTO_RELOAD(pwm_id);
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else
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tcon |= TCON4_AUTO_RELOAD;
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writel(tcon, &pwm->tcon);
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tcon &= ~TCON_UPDATE(pwm_id);
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writel(tcon, &pwm->tcon);
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return 0;
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}
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int pwm_init(int pwm_id, int div, int invert)
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{
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u32 val;
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const struct s5p_timer *pwm =
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(struct s5p_timer *)samsung_get_base_timer();
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unsigned long ticks_per_period;
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unsigned int offset, prescaler;
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/*
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* Timer Freq(HZ) =
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* PWM_CLK / { (prescaler_value + 1) * (divider_value) }
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*/
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val = readl(&pwm->tcfg0);
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if (pwm_id < 2) {
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prescaler = PRESCALER_0;
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val &= ~0xff;
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val |= (prescaler & 0xff);
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} else {
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prescaler = PRESCALER_1;
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val &= ~(0xff << 8);
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val |= (prescaler & 0xff) << 8;
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}
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writel(val, &pwm->tcfg0);
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val = readl(&pwm->tcfg1);
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val &= ~(0xf << MUX_DIV_SHIFT(pwm_id));
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val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id);
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writel(val, &pwm->tcfg1);
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if (pwm_id == 4) {
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/*
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* TODO(sjg): Use this as a countdown timer for now. We count
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* down from the maximum value to 0, then reset.
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*/
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ticks_per_period = -1UL;
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} else {
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const unsigned long pwm_hz = 1000;
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unsigned long timer_rate_hz = get_pwm_clk() /
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((prescaler + 1) * (1 << div));
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ticks_per_period = timer_rate_hz / pwm_hz;
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}
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/* set count value */
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offset = pwm_id * 3;
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writel(ticks_per_period, &pwm->tcntb0 + offset);
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val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id));
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if (invert && (pwm_id < 4))
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val |= TCON_INVERTER(pwm_id);
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writel(val, &pwm->tcon);
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pwm_enable(pwm_id);
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return 0;
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}
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