mirror of
https://github.com/AsahiLinux/u-boot
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d4b1b52737
Moving arch/arm/mach-litesom/ to arch/arm/cpu/armv7/mx6/ was requested in [1] during discussion of chiliSOM support patches. [1] http://lists.denx.de/pipermail/u-boot/2017-January/279137.html Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
287 lines
6.4 KiB
C
287 lines
6.4 KiB
C
/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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* Copyright (C) 2016 Grinn
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/litesom.h>
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#include <asm/arch/mx6ul_pins.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/io.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <linux/sizes.h>
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#include <linux/fb.h>
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#include <miiphy.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <spl.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const sd_pads[] = {
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* CD */
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MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#ifdef CONFIG_FEC_MXC
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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}
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#endif
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
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#define SD_CD_GPIO IMX_GPIO_NR(1, 19)
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static int mmc_get_env_devno(void)
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{
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u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
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int dev_no;
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u32 bootsel;
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bootsel = (soc_sbmr & 0x000000FF) >> 6;
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/* If not boot from sd/mmc, use default value */
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if (bootsel != 1)
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return CONFIG_SYS_MMC_ENV_DEV;
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/* BOOT_CFG2[3] and BOOT_CFG2[4] */
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dev_no = (soc_sbmr & 0x00001800) >> 11;
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return dev_no;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(SD_CD_GPIO);
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break;
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case USDHC2_BASE_ADDR:
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ret = 1;
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int ret;
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/* SD */
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imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
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gpio_direction_input(SD_CD_GPIO);
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sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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ret = fsl_esdhc_initialize(bis, &sd_cfg);
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if (ret) {
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printf("Warning: failed to initialize mmc dev 0 (SD)\n");
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return ret;
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}
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return litesom_mmc_init(bis);
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}
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static int check_mmc_autodetect(void)
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{
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char *autodetect_str = getenv("mmcautodetect");
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if ((autodetect_str != NULL) &&
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(strcmp(autodetect_str, "yes") == 0)) {
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return 1;
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}
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return 0;
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}
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void board_late_mmc_init(void)
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{
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char cmd[32];
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char mmcblk[32];
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u32 dev_no = mmc_get_env_devno();
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if (!check_mmc_autodetect())
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return;
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setenv_ulong("mmcdev", dev_no);
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/* Set mmcblk env */
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sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
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dev_no);
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setenv("mmcroot", mmcblk);
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sprintf(cmd, "mmc dev %d", dev_no);
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run_command(cmd, 0);
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}
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#endif
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#ifdef CONFIG_FEC_MXC
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int board_eth_init(bd_t *bis)
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{
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setup_iomux_fec();
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return fecmxc_initialize(bis);
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}
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static int setup_fec(void)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
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set gpr1[17]*/
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
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IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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return ret;
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enable_enet_clk(1);
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return 0;
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}
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#endif
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#ifdef CONFIG_USB_EHCI_MX6
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int board_usb_phy_mode(int port)
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{
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return USB_INIT_HOST;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
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{"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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int board_late_init(void)
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{
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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#ifdef CONFIG_ENV_IS_IN_MMC
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board_late_mmc_init();
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#endif
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Grinn liteBoard\n");
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void board_boot_order(u32 *spl_boot_list)
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{
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
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unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
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unsigned port = (reg >> 11) & 0x1;
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if (port == 0) {
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spl_boot_list[0] = BOOT_DEVICE_MMC1;
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spl_boot_list[1] = BOOT_DEVICE_MMC2;
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} else {
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spl_boot_list[0] = BOOT_DEVICE_MMC2;
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spl_boot_list[1] = BOOT_DEVICE_MMC1;
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}
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}
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void board_init_f(ulong dummy)
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{
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litesom_init_f();
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}
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#endif
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