Roger Quadros 6887f8e00b arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge ... NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This fixup is critical to provide deterministic access latency to MSMC from ICSSG, it applies to all AM65 silicon revisions and is due to incorrect reset values (has no erratum id) and statically setting things up should be done independent of usecases and board. This specific style of Northbridge configuration is specific only to AM65x devices, follow-on K3 devices have different data prioritization schemes (ASEL and the like) and hence the fixup applies purely to AM65x. Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in case of SR1 devices, on SR2 devices, lockups were not observed so far but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower throughput. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Andrew F. Davis <afd@ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Benoit Parrot <bparrot@ti.com> [Jan: rebased, dropped used define, extended commit log] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> [Nishanth: Provide relevant context in the commit message] Signed-off-by: Nishanth Menon<nm@ti.com>		2021-09-17 14:47:03 -04:00
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mach	arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge	2021-09-17 14:47:03 -04:00