mirror of
https://github.com/AsahiLinux/u-boot
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571c49789d
Sync the serial nodes of the LS1088A based boards with their representation in Linux. We also imported the clockgen and sysclk nodes which are dependencies. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
194 lines
3.1 KiB
Text
194 lines
3.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls1088a QDS common board device tree source
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*
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* Copyright 2017-2020 NXP
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*/
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#include "fsl-ls1088a.dtsi"
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/ {
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aliases {
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spi0 = &qspi;
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spi1 = &dspi;
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};
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};
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&emdio1 {
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status = "okay";
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};
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&emdio2 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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bootph-all;
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fpga@66 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "simple-mfd";
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reg = <0x66>;
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mux-mdio@54 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-i2creg";
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reg = <0x54>;
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#mux-control-cells = <1>;
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mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5
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mdio-parent-bus = <&emdio1>;
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mdio@00 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00>;
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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mdio@20 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x20>;
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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emdio1_slot1: mdio@40 { /* I/O Slot #1 */
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reg = <0x40>;
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device-name = "emdio1_slot1";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emdio1_slot3: mdio@60 { /* I/O Slot #3 */
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reg = <0x60>;
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device-name = "emdio1_slot3";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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i2c-mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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rtc@51 {
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compatible = "nxp,pcf2129";
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reg = <0x51>;
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};
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};
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0 0 0x5 0x80000000 0x08000000
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2 0 0x5 0x30000000 0x00010000
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3 0 0x5 0x20000000 0x00010000>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@2,0 {
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compatible = "fsl,ifc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1 0x0 0x10000>;
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};
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fpga: board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus", "fsl,ls1088aqds-fpga",
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"fsl,fpga-qixis";
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reg = <0x2 0x0 0x0000100>;
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bank-width = <1>;
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device-width = <1>;
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ranges = <0 2 0 0x100>;
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&dspi {
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bus-num = <0>;
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status = "okay";
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dflash0: n25q128a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <1000000>; /* input clock */
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};
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dflash1: sst25wf040b {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <3500000>;
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reg = <1>;
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};
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dflash2: en25s64 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <3500000>;
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reg = <2>;
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};
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};
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&qspi {
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status = "okay";
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s25fs512s0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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s25fs512s1: flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <1>;
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};
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};
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&sata {
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status = "okay";
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};
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