mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
b04c21afd6
The AC5/AC5X SoC has a NAND flash controller. Add this to the SoC device tree. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
286 lines
6.1 KiB
Text
286 lines
6.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Device Tree For AC5.
|
|
*
|
|
* Copyright (C) 2021 Marvell
|
|
* Copyright (C) 2022 Allied Telesis Labs
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
model = "Marvell AC5 SoC";
|
|
compatible = "marvell,ac5";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&cpu0>;
|
|
};
|
|
core1 {
|
|
cpu = <&cpu1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x100>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
l2: l2-cache {
|
|
compatible = "cache";
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
dma-ranges;
|
|
|
|
internal-regs@7f000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "simple-bus";
|
|
/* 16M internal register @ 0x7f00_0000 */
|
|
ranges = <0x0 0x0 0x7f000000 0x1000000>;
|
|
dma-coherent;
|
|
|
|
uart0: serial@12000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x12000 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-io-width = <1>;
|
|
clocks = <&cnm_clock>;
|
|
status = "okay";
|
|
};
|
|
|
|
uart1: serial@12100 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x12100 0x100>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <1>;
|
|
clocks = <&cnm_clock>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@12200 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x12200 0x100>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <1>;
|
|
clocks = <&cnm_clock>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@12300 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x12300 0x100>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <1>;
|
|
clocks = <&cnm_clock>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio: mdio@22004 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "marvell,orion-mdio";
|
|
reg = <0x22004 0x4>;
|
|
clocks = <&cnm_clock>;
|
|
};
|
|
|
|
i2c0: i2c@11000 {
|
|
compatible = "marvell,mv78230-i2c";
|
|
reg = <0x11000 0x20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clocks = <&cnm_clock>;
|
|
clock-names = "core";
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency=<100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@11100 {
|
|
compatible = "marvell,mv78230-i2c";
|
|
reg = <0x11100 0x20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
clocks = <&cnm_clock>;
|
|
clock-names = "core";
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency=<100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio0: gpio@18100 {
|
|
compatible = "marvell,orion-gpio";
|
|
reg = <0x18100 0x40>;
|
|
ngpios = <32>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
status = "okay";
|
|
};
|
|
|
|
gpio1: gpio@18140 {
|
|
reg = <0x18140 0x40>;
|
|
compatible = "marvell,orion-gpio";
|
|
ngpios = <14>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
/*
|
|
* Dedicated section for devices behind 32bit controllers so we
|
|
* can configure specific DMA mapping for them
|
|
*/
|
|
behind-32bit-controller@7f000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x2>;
|
|
ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
|
|
/* Host phy ram starts at 0x200M */
|
|
dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
|
|
dma-coherent;
|
|
|
|
eth0: ethernet@20000 {
|
|
compatible = "marvell,armada-ac5-neta";
|
|
reg = <0x0 0x20000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cnm_clock>;
|
|
phy-mode = "sgmii";
|
|
status = "disabled";
|
|
};
|
|
|
|
eth1: ethernet@24000 {
|
|
compatible = "marvell,armada-ac5-neta";
|
|
reg = <0x0 0x24000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cnm_clock>;
|
|
phy-mode = "sgmii";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb0: usb@80000 {
|
|
compatible = "marvell,ac5-ehci";
|
|
reg = <0x0 0x80000 0x0 0x500>;
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb1: usb@a0000 {
|
|
compatible = "marvell,ac5-ehci";
|
|
reg = <0x0 0xa0000 0x0 0x500>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pinctrl0: pinctrl@80020100 {
|
|
compatible = "marvell,mvebu-pinctrl";
|
|
reg = <0 0x80020100 0 0x20>;
|
|
pin-count = <46>;
|
|
max-func = <0xf>;
|
|
status = "okay";
|
|
};
|
|
|
|
spi0: spi@805a0000 {
|
|
compatible = "marvell,armada-3700-spi";
|
|
reg = <0x0 0x805a0000 0x0 0x50>;
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
clocks = <&spi_clock>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
num-cs = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@805a8000 {
|
|
compatible = "marvell,armada-3700-spi";
|
|
reg = <0x0 0x805a8000 0x0 0x50>;
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
clocks = <&spi_clock>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
num-cs = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
nand: nand-controller@805b0000 {
|
|
compatible = "marvell,mvebu-ac5-pxa3xx-nand";
|
|
reg = <0x0 0x805b0000 0x0 0x54>;
|
|
#address-cells = <0x00000001>;
|
|
marvell,nand-enable-arbiter;
|
|
num-cs = <0x00000001>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@80600000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
|
|
<0x0 0x80660000 0x0 0x40000>; /* GICR */
|
|
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
cnm_clock: cnm-clock {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <328000000>;
|
|
};
|
|
|
|
spi_clock: spi-clock {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <200000000>;
|
|
};
|
|
};
|
|
};
|