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https://github.com/AsahiLinux/u-boot
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c8c41d4a80
We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE. While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only be used for configuring the PCI ATMU. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
120 lines
3.7 KiB
ArmAsm
120 lines
3.7 KiB
ArmAsm
/*
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* Copyright (C) 2002,2003, Motorola Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
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* Added support for Wind River SBC8560 board
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc85xx.h>
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#define entry_start \
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mflr r1 ; \
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bl 0f ;
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#define entry_end \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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/* TLB1 entries configuration: */
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.section .bootpg, "ax"
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.globl tlb1_entry
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tlb1_entry:
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entry_start
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.long 0x08 /* the following data table uses a few of 16 TLB entries */
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/* TLB for CCSRBAR (IMMR) */
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.long FSL_BOOKE_MAS0(1,1,0)
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.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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/* TLB for Local Bus stuff, just map the whole 512M */
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/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
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.long FSL_BOOKE_MAS0(1,2,0)
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.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(0xe0000000,(MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(0xe0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(1,3,0)
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.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(0xf0000000,(MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(0xf0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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#if !defined(CONFIG_SPD_EEPROM)
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.long FSL_BOOKE_MAS0(1,4,0)
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.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0)
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.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(1,5,0)
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.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000,0)
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.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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#else
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.long FSL_BOOKE_MAS0(1,4,0)
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.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
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.long FSL_BOOKE_MAS2(0,0)
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.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(1,5,0)
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.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
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.long FSL_BOOKE_MAS2(0,0)
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.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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#endif
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.long FSL_BOOKE_MAS0(1,6,0)
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.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
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#ifdef CONFIG_L2_INIT_RAM
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0)
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#else
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0)
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#endif
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(1,7,0)
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.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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.long FSL_BOOKE_MAS0(1,15,0)
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.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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#else
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.long FSL_BOOKE_MAS0(1,15,0)
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.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
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.long FSL_BOOKE_MAS2(0,0)
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.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
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#endif
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entry_end
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