mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
3e0b196696
Sync the devicetree files used in the kernel for the imx8mm-phyboard-polis with the corresponding devicetree files in U-Boot. Replaced phycore-imx8mm.dts with kernel dts imx8mm-phyboard-polis-rdk.dts Synced with kernel 6.5.0-rc1 commit e752a4f9589c (arm64: dts: freescale: imx8mm-phyboard: Add I2C4 pinmuxing) Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
460 lines
10 KiB
Text
460 lines
10 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mm-phycore-som.dtsi"
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/ {
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model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
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compatible = "phytec,imx8mm-phyboard-polis-rdk",
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"phytec,imx8mm-phycore-som", "fsl,imx8mm";
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chosen {
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stdout-path = &uart3;
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};
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bt_osc_32k: bt-lp-clock {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "bt_osc_32k";
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#clock-cells = <0>;
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};
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can_osc_40m: can-clock {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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clock-output-names = "can_osc_40m";
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#clock-cells = <0>;
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};
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fan {
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compatible = "gpio-fan";
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gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
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gpio-fan,speed-map = <0 0
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13000 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fan>;
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#cooling-cells = <2>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_leds>;
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led-0 {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_DISK;
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gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc2";
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};
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led-1 {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_DISK;
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gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc1";
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};
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led-2 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_CPU;
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gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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usdhc1_pwrseq: pwr-seq {
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compatible = "mmc-pwrseq-simple";
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post-power-on-delay-ms = <100>;
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power-off-delay-us = <60>;
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reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
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};
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reg_can_en: regulator-can-en {
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compatible = "regulator-fixed";
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gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can_en>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "CAN_EN";
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startup-delay-us = <20>;
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};
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reg_usb_otg1_vbus: regulator-usb-otg1 {
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compatible = "regulator-fixed";
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gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1pwrgrp>;
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regulator-name = "usb_otg1_vbus";
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regulator-max-microvolt = <5000000>;
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regulator-min-microvolt = <5000000>;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <20000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "VSD_3V3";
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};
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reg_vcc_3v3: regulator-vcc-3v3 {
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compatible = "regulator-fixed";
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "VCC_3V3";
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};
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};
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/* SPI - CAN MCP251XFD */
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&ecspi1 {
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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status = "okay";
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can0: can@0 {
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compatible = "microchip,mcp251xfd";
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clocks = <&can_osc_40m>;
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interrupt-parent = <&gpio1>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can_int>;
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reg = <0>;
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spi-max-frequency = <20000000>;
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xceiver-supply = <®_can_en>;
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};
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};
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&gpio1 {
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gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT",
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"", "", "", "RESET_ETHPHY",
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"CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "",
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"USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE";
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};
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&gpio2 {
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gpio-line-names = "", "", "", "",
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"", "", "BT_REG_ON", "WL_REG_ON",
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"BT_DEV_WAKE", "BT_HOST_WAKE", "", "",
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"X_SD2_CD_B", "", "", "",
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"", "", "", "SD2_RESET_B";
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};
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&gpio4 {
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gpio-line-names = "", "", "", "",
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"", "", "", "",
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"FAN", "miniPCIe_nPERST", "", "",
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"COEX1", "COEX2";
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};
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&gpio5 {
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gpio-line-names = "", "", "", "",
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"", "", "", "",
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"", "ECSPI1_SS0";
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};
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&i2c4 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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};
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/* PCIe */
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&pcie0 {
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assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
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<&clk IMX8MM_CLK_PCIE1_CTRL>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
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<&clk IMX8MM_SYS_PLL2_250M>;
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assigned-clock-rates = <10000000>, <250000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie>;
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reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie_phy {
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clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
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fsl,clkreq-unsupported;
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
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fsl,tx-deemph-gen1 = <0x2d>;
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fsl,tx-deemph-gen2 = <0xf>;
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status = "okay";
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};
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&rv3028 {
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trickle-resistor-ohms = <3000>;
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};
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&snvs_pwrkey {
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status = "okay";
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};
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/* UART - RS232/RS485 */
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&uart1 {
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assigned-clocks = <&clk IMX8MM_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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uart-has-rtscts;
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status = "okay";
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};
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/* UART - Sterling-LWB Bluetooth */
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&uart2 {
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assigned-clocks = <&clk IMX8MM_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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fsl,dte-mode;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_bt>;
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uart-has-rtscts;
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status = "okay";
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bluetooth {
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compatible = "brcm,bcm43438-bt";
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clocks = <&bt_osc_32k>;
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clock-names = "lpo";
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device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
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interrupt-names = "host-wakeup";
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interrupt-parent = <&gpio2>;
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interrupts = <9 IRQ_TYPE_EDGE_BOTH>;
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max-speed = <2000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_bt>;
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shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
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vddio-supply = <®_vcc_3v3>;
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};
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};
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/* UART - console */
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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/* USB */
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&usbotg1 {
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adp-disable;
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dr_mode = "otg";
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over-current-active-low;
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samsung,picophy-pre-emp-curr-control = <3>;
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samsung,picophy-dc-vol-level-adjust = <7>;
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srp-disable;
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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disable-over-current;
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dr_mode = "host";
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samsung,picophy-pre-emp-curr-control = <3>;
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samsung,picophy-dc-vol-level-adjust = <7>;
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status = "okay";
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};
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/* SDIO - Sterling-LWB Wifi */
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&usdhc1 {
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assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
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assigned-clock-rates = <200000000>;
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bus-width = <4>;
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mmc-pwrseq = <&usdhc1_pwrseq>;
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non-removable;
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no-1-8-v;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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brcmf: wifi@1 {
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compatible = "brcm,bcm4329-fmac";
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reg = <1>;
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};
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};
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/* SD-Card */
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&usdhc2 {
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assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
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assigned-clock-rates = <200000000>;
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bus-width = <4>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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disable-wp;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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vmmc-supply = <®_usdhc2_vmmc>;
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vqmmc-supply = <®_nvcc_sd2>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_bt: btgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00
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MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00
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MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00
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>;
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};
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pinctrl_can_en: can-engrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00
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>;
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};
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pinctrl_can_int: can-intgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80
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MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80
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MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80
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MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00
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>;
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};
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pinctrl_fan: fan0grp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2
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MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2
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>;
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};
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pinctrl_leds: leds1grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
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MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
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MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16
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>;
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};
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pinctrl_pcie: pciegrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00
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MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12
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MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00
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MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00
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MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00
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MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00
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>;
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};
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pinctrl_uart2_bt: uart2btgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00
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MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00
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MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00
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MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
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MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
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>;
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};
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pinctrl_usbotg1pwrgrp: usbotg1pwrgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182
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MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6
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MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6
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MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6
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MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6
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MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
|
>;
|
|
};
|
|
|
|
pinctrl_wlan: wlangrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00
|
|
>;
|
|
};
|
|
};
|