mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
d0edce4fa3
Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren <twarren@nvidia.com>
48 lines
1.5 KiB
C
48 lines
1.5 KiB
C
/*
|
|
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
/* Tegra cache routines */
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch-tegra/ap.h>
|
|
#include <asm/arch/gp_padctrl.h>
|
|
|
|
void config_cache(void)
|
|
{
|
|
struct apb_misc_gp_ctlr *gp =
|
|
(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
|
|
u32 reg = 0;
|
|
|
|
/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
|
|
asm volatile(
|
|
"mrc p15, 0, r0, c1, c0, 1\n"
|
|
"orr r0, r0, #0x41\n"
|
|
"mcr p15, 0, r0, c1, c0, 1\n");
|
|
|
|
/* Currently, only T114 needs this L2 cache change to boot Linux */
|
|
reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
|
|
if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
|
|
return;
|
|
/*
|
|
* Systems with an architectural L2 cache must not use the PL310.
|
|
* Config L2CTLR here for a data RAM latency of 3 cycles.
|
|
*/
|
|
asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
|
|
reg &= ~7;
|
|
reg |= 2;
|
|
asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
|
|
}
|