mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 17:41:08 +00:00
5fb0151697
Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
241 lines
5 KiB
Text
241 lines
5 KiB
Text
/*
|
|
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include <dt-bindings/gpio/x86-gpio.h>
|
|
#include <dt-bindings/interrupt-router/intel-irq.h>
|
|
|
|
/include/ "skeleton.dtsi"
|
|
/include/ "serial.dtsi"
|
|
/include/ "rtc.dtsi"
|
|
|
|
/ {
|
|
model = "Intel Bayley Bay";
|
|
compatible = "intel,bayleybay", "intel,baytrail";
|
|
|
|
aliases {
|
|
serial0 = &serial;
|
|
spi0 = "/spi";
|
|
};
|
|
|
|
config {
|
|
silent_console = <0>;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "/serial";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "intel,baytrail-cpu";
|
|
reg = <0>;
|
|
intel,apic-id = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "intel,baytrail-cpu";
|
|
reg = <1>;
|
|
intel,apic-id = <2>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "intel,baytrail-cpu";
|
|
reg = <2>;
|
|
intel,apic-id = <4>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "intel,baytrail-cpu";
|
|
reg = <3>;
|
|
intel,apic-id = <6>;
|
|
};
|
|
};
|
|
|
|
spi {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "intel,ich-spi";
|
|
spi-flash@0 {
|
|
reg = <0>;
|
|
compatible = "winbond,w25q64dw", "spi-flash";
|
|
memory-map = <0xff800000 0x00800000>;
|
|
};
|
|
};
|
|
|
|
gpioa {
|
|
compatible = "intel,ich6-gpio";
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0 0x20>;
|
|
bank-name = "A";
|
|
};
|
|
|
|
gpiob {
|
|
compatible = "intel,ich6-gpio";
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0x20 0x20>;
|
|
bank-name = "B";
|
|
};
|
|
|
|
gpioc {
|
|
compatible = "intel,ich6-gpio";
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0x40 0x20>;
|
|
bank-name = "C";
|
|
};
|
|
|
|
gpiod {
|
|
compatible = "intel,ich6-gpio";
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0x60 0x20>;
|
|
bank-name = "D";
|
|
};
|
|
|
|
gpioe {
|
|
compatible = "intel,ich6-gpio";
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0x80 0x20>;
|
|
bank-name = "E";
|
|
};
|
|
|
|
gpiof {
|
|
compatible = "intel,ich6-gpio";
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0xA0 0x20>;
|
|
bank-name = "F";
|
|
};
|
|
|
|
pci {
|
|
compatible = "pci-x86";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
u-boot,dm-pre-reloc;
|
|
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
|
|
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
|
|
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
|
|
|
|
irq-router@1f,0 {
|
|
reg = <0x0000f800 0 0 0 0>;
|
|
compatible = "intel,irq-router";
|
|
intel,pirq-config = "ibase";
|
|
intel,ibase-offset = <0x50>;
|
|
intel,pirq-link = <8 8>;
|
|
intel,pirq-mask = <0xdee0>;
|
|
intel,pirq-routing = <
|
|
/* BayTrail PCI devices */
|
|
PCI_BDF(0, 2, 0) INTA PIRQA
|
|
PCI_BDF(0, 3, 0) INTA PIRQA
|
|
PCI_BDF(0, 16, 0) INTA PIRQA
|
|
PCI_BDF(0, 17, 0) INTA PIRQA
|
|
PCI_BDF(0, 18, 0) INTA PIRQA
|
|
PCI_BDF(0, 19, 0) INTA PIRQA
|
|
PCI_BDF(0, 20, 0) INTA PIRQA
|
|
PCI_BDF(0, 21, 0) INTA PIRQA
|
|
PCI_BDF(0, 22, 0) INTA PIRQA
|
|
PCI_BDF(0, 23, 0) INTA PIRQA
|
|
PCI_BDF(0, 24, 0) INTA PIRQA
|
|
PCI_BDF(0, 24, 1) INTC PIRQC
|
|
PCI_BDF(0, 24, 2) INTD PIRQD
|
|
PCI_BDF(0, 24, 3) INTB PIRQB
|
|
PCI_BDF(0, 24, 4) INTA PIRQA
|
|
PCI_BDF(0, 24, 5) INTC PIRQC
|
|
PCI_BDF(0, 24, 6) INTD PIRQD
|
|
PCI_BDF(0, 24, 7) INTB PIRQB
|
|
PCI_BDF(0, 26, 0) INTA PIRQA
|
|
PCI_BDF(0, 27, 0) INTA PIRQA
|
|
PCI_BDF(0, 28, 0) INTA PIRQA
|
|
PCI_BDF(0, 28, 1) INTB PIRQB
|
|
PCI_BDF(0, 28, 2) INTC PIRQC
|
|
PCI_BDF(0, 28, 3) INTD PIRQD
|
|
PCI_BDF(0, 29, 0) INTA PIRQA
|
|
PCI_BDF(0, 30, 0) INTA PIRQA
|
|
PCI_BDF(0, 30, 1) INTD PIRQD
|
|
PCI_BDF(0, 30, 2) INTB PIRQB
|
|
PCI_BDF(0, 30, 3) INTC PIRQC
|
|
PCI_BDF(0, 30, 4) INTD PIRQD
|
|
PCI_BDF(0, 30, 5) INTB PIRQB
|
|
PCI_BDF(0, 31, 3) INTB PIRQB
|
|
|
|
/* PCIe root ports downstream interrupts */
|
|
PCI_BDF(1, 0, 0) INTA PIRQA
|
|
PCI_BDF(1, 0, 0) INTB PIRQB
|
|
PCI_BDF(1, 0, 0) INTC PIRQC
|
|
PCI_BDF(1, 0, 0) INTD PIRQD
|
|
PCI_BDF(2, 0, 0) INTA PIRQB
|
|
PCI_BDF(2, 0, 0) INTB PIRQC
|
|
PCI_BDF(2, 0, 0) INTC PIRQD
|
|
PCI_BDF(2, 0, 0) INTD PIRQA
|
|
PCI_BDF(3, 0, 0) INTA PIRQC
|
|
PCI_BDF(3, 0, 0) INTB PIRQD
|
|
PCI_BDF(3, 0, 0) INTC PIRQA
|
|
PCI_BDF(3, 0, 0) INTD PIRQB
|
|
PCI_BDF(4, 0, 0) INTA PIRQD
|
|
PCI_BDF(4, 0, 0) INTB PIRQA
|
|
PCI_BDF(4, 0, 0) INTC PIRQB
|
|
PCI_BDF(4, 0, 0) INTD PIRQC
|
|
>;
|
|
};
|
|
};
|
|
|
|
fsp {
|
|
compatible = "intel,baytrail-fsp";
|
|
fsp,mrc-init-tseg-size = <0>;
|
|
fsp,mrc-init-mmio-size = <0x800>;
|
|
fsp,mrc-init-spd-addr1 = <0xa0>;
|
|
fsp,mrc-init-spd-addr2 = <0xa2>;
|
|
fsp,emmc-boot-mode = <2>;
|
|
fsp,enable-sdio;
|
|
fsp,enable-sdcard;
|
|
fsp,enable-hsuart1;
|
|
fsp,enable-spi;
|
|
fsp,enable-sata;
|
|
fsp,sata-mode = <1>;
|
|
fsp,enable-lpe;
|
|
fsp,lpss-sio-enable-pci-mode;
|
|
fsp,enable-dma0;
|
|
fsp,enable-dma1;
|
|
fsp,enable-i2c0;
|
|
fsp,enable-i2c1;
|
|
fsp,enable-i2c2;
|
|
fsp,enable-i2c3;
|
|
fsp,enable-i2c4;
|
|
fsp,enable-i2c5;
|
|
fsp,enable-i2c6;
|
|
fsp,enable-pwm0;
|
|
fsp,enable-pwm1;
|
|
fsp,igd-dvmt50-pre-alloc = <2>;
|
|
fsp,aperture-size = <2>;
|
|
fsp,gtt-size = <2>;
|
|
fsp,serial-debug-port-address = <0x3f8>;
|
|
fsp,serial-debug-port-type = <1>;
|
|
fsp,scc-enable-pci-mode;
|
|
fsp,os-selection = <4>;
|
|
fsp,emmc45-ddr50-enabled;
|
|
fsp,emmc45-retune-timer-value = <8>;
|
|
fsp,enable-igd;
|
|
};
|
|
|
|
microcode {
|
|
update@0 {
|
|
#include "microcode/m0230671117.dtsi"
|
|
};
|
|
update@1 {
|
|
#include "microcode/m0130673322.dtsi"
|
|
};
|
|
update@2 {
|
|
#include "microcode/m0130679901.dtsi"
|
|
};
|
|
};
|
|
|
|
};
|