mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 22:33:18 +00:00
a09fea1d28
- In ARMv8 NXP Layerscape platforms we also need to make use of CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so. - On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define to 0. - Add Kconfig entry for ENV_ADDR. - Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it. - Add ENV_xxx_REDUND options that depend on their primary option and SYS_REDUNDAND_ENVIRONMENT - On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR for the pre-main-U-Boot environment location. - On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but rather it being non-zero, as it will now be zero by default. - Rework the env_offset absolute in env/embedded.o to not use CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within ENV_IS_IN_FLASH. - Migrate all platforms. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
177 lines
4.6 KiB
Text
177 lines
4.6 KiB
Text
CONFIG_PPC=y
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CONFIG_SYS_TEXT_BASE=0xFE000000
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CONFIG_ENV_SIZE=0x4000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_SYS_CLK_FREQ=66666667
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CONFIG_MPC83xx=y
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CONFIG_HIGH_BATS=y
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CONFIG_TARGET_MPC837XERDB=y
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CONFIG_DDR_MC_CLOCK_MODE_1_1=y
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CONFIG_SYSTEM_PLL_FACTOR_5_1=y
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CONFIG_CORE_PLL_RATIO_2_1=y
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CONFIG_PCI_HOST_MODE_ENABLE=y
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CONFIG_PCI_INT_ARBITER1_ENABLE=y
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CONFIG_BOOT_MEMORY_SPACE_LOW=y
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CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
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CONFIG_TSEC1_MODE_RGMII=y
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CONFIG_TSEC2_MODE_RGMII=y
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CONFIG_LDP_PIN_MUX_STATE_0=y
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CONFIG_BAT0=y
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CONFIG_BAT0_NAME="SDRAM_LOWER"
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CONFIG_BAT0_BASE=0x00000000
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CONFIG_BAT0_LENGTH_256_MBYTES=y
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CONFIG_BAT0_ACCESS_RW=y
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CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
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CONFIG_BAT0_USER_MODE_VALID=y
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CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT1=y
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CONFIG_BAT1_NAME="SDRAM_UPPER"
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CONFIG_BAT1_BASE=0x10000000
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CONFIG_BAT1_LENGTH_256_MBYTES=y
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CONFIG_BAT1_ACCESS_RW=y
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CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y
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CONFIG_BAT1_USER_MODE_VALID=y
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CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT2=y
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CONFIG_BAT2_NAME="IMMR"
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CONFIG_BAT2_BASE=0xE0000000
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CONFIG_BAT2_LENGTH_8_MBYTES=y
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CONFIG_BAT2_ACCESS_RW=y
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CONFIG_BAT2_ICACHE_INHIBITED=y
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CONFIG_BAT2_ICACHE_GUARDED=y
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CONFIG_BAT2_DCACHE_INHIBITED=y
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CONFIG_BAT2_DCACHE_GUARDED=y
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CONFIG_BAT2_USER_MODE_VALID=y
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CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT3=y
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CONFIG_BAT3_NAME="L2_SWITCH"
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CONFIG_BAT3_BASE=0xF0000000
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CONFIG_BAT3_ACCESS_RW=y
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CONFIG_BAT3_ICACHE_INHIBITED=y
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CONFIG_BAT3_ICACHE_GUARDED=y
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CONFIG_BAT3_DCACHE_INHIBITED=y
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CONFIG_BAT3_DCACHE_GUARDED=y
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CONFIG_BAT3_USER_MODE_VALID=y
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CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT4=y
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CONFIG_BAT4_NAME="FLASH"
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CONFIG_BAT4_BASE=0xFE000000
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CONFIG_BAT4_LENGTH_32_MBYTES=y
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CONFIG_BAT4_ACCESS_RW=y
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CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT4_DCACHE_INHIBITED=y
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CONFIG_BAT4_DCACHE_GUARDED=y
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CONFIG_BAT4_USER_MODE_VALID=y
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CONFIG_BAT4_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT5=y
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CONFIG_BAT5_NAME="STACH_IN_DCACHE"
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CONFIG_BAT5_BASE=0xE6000000
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CONFIG_BAT5_ACCESS_RW=y
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CONFIG_BAT5_USER_MODE_VALID=y
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CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT6=y
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CONFIG_BAT6_NAME="PCI_MEM"
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CONFIG_BAT6_BASE=0x80000000
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CONFIG_BAT6_LENGTH_256_MBYTES=y
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CONFIG_BAT6_ACCESS_RW=y
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CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
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CONFIG_BAT6_USER_MODE_VALID=y
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CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT7=y
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CONFIG_BAT7_NAME="PCI_MMIO"
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CONFIG_BAT7_BASE=0x90000000
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CONFIG_BAT7_LENGTH_256_MBYTES=y
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CONFIG_BAT7_ACCESS_RW=y
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CONFIG_BAT7_ICACHE_INHIBITED=y
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CONFIG_BAT7_ICACHE_GUARDED=y
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CONFIG_BAT7_DCACHE_INHIBITED=y
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CONFIG_BAT7_DCACHE_GUARDED=y
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CONFIG_BAT7_USER_MODE_VALID=y
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CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
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CONFIG_LBLAW0=y
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CONFIG_LBLAW0_BASE=0xFE000000
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CONFIG_LBLAW0_NAME="FLASH"
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CONFIG_LBLAW0_LENGTH_8_MBYTES=y
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CONFIG_LBLAW1=y
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CONFIG_LBLAW1_BASE=0xE0600000
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CONFIG_LBLAW1_NAME="NAND"
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CONFIG_LBLAW1_LENGTH_32_KBYTES=y
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CONFIG_LBLAW2=y
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CONFIG_LBLAW2_BASE=0xF0000000
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CONFIG_LBLAW2_NAME="VSC7385"
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CONFIG_LBLAW2_LENGTH_128_KBYTES=y
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CONFIG_ELBC_BR0_OR0=y
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CONFIG_BR0_OR0_NAME="FLASH"
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CONFIG_BR0_OR0_BASE=0xFE000000
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CONFIG_BR0_PORTSIZE_16BIT=y
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CONFIG_OR0_AM_8_MBYTES=y
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CONFIG_OR0_SCY_9=y
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CONFIG_OR0_XACS_EXTENDED=y
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CONFIG_OR0_EHTR_1_CYCLE=y
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CONFIG_OR0_EAD_EXTRA=y
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CONFIG_ELBC_BR1_OR1=y
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CONFIG_BR1_OR1_NAME="NAND"
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CONFIG_BR1_OR1_BASE=0xE0600000
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CONFIG_BR1_ERRORCHECKING_BOTH=y
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CONFIG_BR1_MACHINE_FCM=y
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CONFIG_OR1_SCY_1=y
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CONFIG_OR1_CSCT_8_CYCLE=y
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CONFIG_OR1_CST_ONE_CLOCK=y
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CONFIG_OR1_CHT_TWO_CLOCK=y
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CONFIG_OR1_TRLX_RELAXED=y
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CONFIG_OR1_EHTR_8_CYCLE=y
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CONFIG_ELBC_BR2_OR2=y
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CONFIG_BR2_OR2_NAME="VSC7385"
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CONFIG_BR2_OR2_BASE=0xF0000000
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CONFIG_OR2_AM_128_KBYTES=y
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CONFIG_OR2_SCY_15=y
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CONFIG_OR2_CSNT_EARLIER=y
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CONFIG_OR2_XACS_EXTENDED=y
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CONFIG_OR2_SETA_EXTERNAL=y
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CONFIG_OR2_TRLX_RELAXED=y
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CONFIG_OR2_EHTR_8_CYCLE=y
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CONFIG_OR2_EAD_EXTRA=y
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CONFIG_HID0_FINAL_EMCP=y
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CONFIG_HID0_FINAL_ICE=y
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CONFIG_HID2_HBE=y
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CONFIG_ACR_PIPE_DEP_4=y
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CONFIG_ACR_RPTCNT_4=y
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CONFIG_SPCR_TSECEP_3=y
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CONFIG_LCRR_DBYP_PLL_BYPASSED=y
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CONFIG_LCRR_CLKDIV_8=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="PCIE"
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CONFIG_BOOTDELAY=6
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CONFIG_MISC_INIT_R=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_SATA=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_DATE=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_ENV_ADDR=0xFE080000
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CONFIG_FSL_SATA=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_PROTECTION=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_PHY_MARVELL=y
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CONFIG_TSEC_ENET=y
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CONFIG_SYS_NS16550=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_OF_LIBFDT=y
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