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e9a20f8a19
Need to increase the LPDDR2/LPDDR3 the voltage vdd2_ddr: buck2 form 1.2V to 1.25V for 32bits configuration. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
112 lines
2.6 KiB
C
112 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#ifndef __PMIC_STPMIC1_H_
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#define __PMIC_STPMIC1_H_
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#define STPMIC1_MAIN_CR 0x10
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#define STPMIC1_BUCKS_MRST_CR 0x18
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#define STPMIC1_LDOS_MRST_CR 0x1a
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#define STPMIC1_BUCKX_MAIN_CR(buck) (0x20 + (buck))
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#define STPMIC1_REFDDR_MAIN_CR 0x24
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#define STPMIC1_LDOX_MAIN_CR(ldo) (0x25 + (ldo))
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#define STPMIC1_BST_SW_CR 0x40
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#define STPMIC1_NVM_SR 0xb8
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#define STPMIC1_NVM_CR 0xb9
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/* Main PMIC Control Register (MAIN_CR) */
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#define STPMIC1_SWOFF BIT(0)
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#define STPMIC1_RREQ_EN BIT(1)
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/* BUCKS_MRST_CR */
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#define STPMIC1_MRST_BUCK(buck) BIT(buck)
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#define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \
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STPMIC1_MRST_BUCK(STPMIC1_BUCK3))
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/* LDOS_MRST_CR */
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#define STPMIC1_MRST_LDO(ldo) BIT(ldo)
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#define STPMIC1_MRST_LDO_DEBUG 0
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/* BUCKx_MAIN_CR (x=1...4) */
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#define STPMIC1_BUCK_ENA BIT(0)
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#define STPMIC1_BUCK_PREG_MODE BIT(1)
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#define STPMIC1_BUCK_VOUT_MASK GENMASK(7, 2)
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#define STPMIC1_BUCK_VOUT_SHIFT 2
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#define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT)
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#define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24)
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#define STPMIC1_BUCK2_1250000V STPMIC1_BUCK_VOUT(26)
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#define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30)
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#define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39)
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/* REFDDR_MAIN_CR */
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#define STPMIC1_VREF_ENA BIT(0)
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/* LDOX_MAIN_CR */
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#define STPMIC1_LDO_ENA BIT(0)
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#define STPMIC1_LDO12356_VOUT_MASK GENMASK(6, 2)
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#define STPMIC1_LDO12356_VOUT_SHIFT 2
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#define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT)
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#define STPMIC1_LDO3_MODE BIT(7)
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#define STPMIC1_LDO3_DDR_SEL 31
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#define STPMIC1_LDO3_1800000 STPMIC1_LDO_VOUT(9)
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#define STPMIC1_LDO4_UV 3300000
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/* BST_SW_CR */
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#define STPMIC1_BST_ON BIT(0)
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#define STPMIC1_VBUSOTG_ON BIT(1)
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#define STPMIC1_SWOUT_ON BIT(2)
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#define STPMIC1_PWR_SW_ON (STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
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/* NVM_SR */
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#define STPMIC1_NVM_BUSY BIT(0)
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/* NVM_CR */
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#define STPMIC1_NVM_CMD_PROGRAM 1
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#define STPMIC1_NVM_CMD_READ 2
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/* Timeout */
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#define STPMIC1_DEFAULT_START_UP_DELAY_MS 1
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#define STPMIC1_DEFAULT_STOP_DELAY_MS 5
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#define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10
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enum {
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STPMIC1_BUCK1,
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STPMIC1_BUCK2,
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STPMIC1_BUCK3,
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STPMIC1_BUCK4,
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STPMIC1_MAX_BUCK,
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};
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enum {
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STPMIC1_PREG_MODE_HP,
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STPMIC1_PREG_MODE_LP,
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};
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enum {
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STPMIC1_LDO1,
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STPMIC1_LDO2,
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STPMIC1_LDO3,
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STPMIC1_LDO4,
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STPMIC1_LDO5,
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STPMIC1_LDO6,
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STPMIC1_MAX_LDO,
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};
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enum {
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STPMIC1_LDO_MODE_NORMAL,
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STPMIC1_LDO_MODE_BYPASS,
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STPMIC1_LDO_MODE_SINK_SOURCE,
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};
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enum {
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STPMIC1_PWR_SW1,
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STPMIC1_PWR_SW2,
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STPMIC1_MAX_PWR_SW,
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};
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#endif
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