u-boot/board/freescale/mx25pdk
Benoît Thébaudeau 747778cf69 mx25pdk: Set the eSDHC PER clock to 48 MHz
The maximum SD clock frequency in High Speed mode is 50 MHz. This change
makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1)
instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2).

Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-05-31 10:14:41 +02:00
..
imximage.cfg Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
Kconfig kconfig: arm: introduce symbol for ARM CPUs 2014-10-29 09:02:09 -04:00
MAINTAINERS MAINTAINERS/mailmap: Update my email address 2016-01-11 11:22:43 -05:00
Makefile mx25pdk: Remove lowlevel_init.S file 2016-01-24 11:52:45 +01:00
mx25pdk.c mx25pdk: Set the eSDHC PER clock to 48 MHz 2017-05-31 10:14:41 +02:00